HBM Chip Stack Heat Dissipation Bump Pitch Variation

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Solution Overview

Problem

High bandwidth memory (HBM) chip stacks experience inefficient heat dissipation, particularly at the central portion where temperatures are higher, due to uniformly spaced heat dissipation bumps, leading to low heat dissipation effectiveness.

Innovation Solution

The semiconductor package design incorporates a varying pitch arrangement for heat dissipation bumps, with a narrower second pitch in the central high-temperature region compared to the edge region, increasing the density of heat dissipation bumps to enhance heat dissipation efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If heat dissipation bumps are arranged by a uniform pitch, then the manufacturing process is simple, but the heat dissipation efficiency is low in the central high-temperature region

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidheat dissipation efficiency
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent applies local quality by dividing the chip surface into different regions (central region and peripheral region) and assigning different heat dissipation bump pitches to each region. The central region uses a first pitch while the peripheral region uses a second pitch, allowing each area to have optimized heat dissipation characteristics according to its local temperature requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the pitch parameter of heat dissipation bumps based on spatial location. By setting different pitch values (first pitch for central region, second pitch for peripheral region), the patent optimizes heat dissipation effectiveness in high-temperature areas while maintaining reasonable manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If heat dissipation bumps are arranged with larger pitch, then the manufacturing is easier, but the heat dissipation effectiveness in central portion is insufficient

Engineering Contradiction:
Improvebump arrangement simplicityVSAvoidheat dissipation effectiveness
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements local quality optimization by configuring heat dissipation bumps with different pitches in different regions. The central region, which generates more heat, uses a first pitch that provides adequate heat dissipation, while the peripheral region uses a second pitch that is easier to manufacture, thus achieving both reliability and ease of manufacture locally.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the chip surface into multiple regions with different heat dissipation requirements and applies different bump pitch configurations to each segment. This segmentation allows the system to balance manufacturing ease and heat dissipation effectiveness by treating different areas independently according to their specific needs.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively dissipates heat generated in the high-temperature regions of the stacked HBM chips, reducing heat resistance and improving overall heat dissipation characteristics of the semiconductor package.

Implementation Method 1

heat dissipation bumps may be arranged between the HBM chips

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS11658160B2Semiconductor package and method of manufacturing the same
Publication Date: 2023.05.23 SAMSUNG ELECTRONICS CO LTD
  • US11658160B2 patent drawing
  • US11658160B2 patent drawing
  • US11658160B2 patent drawing

AI summary

A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.