HBM Chip Stack Layout for Lower Parasitic Interconnects
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Solution Overview
Problem
High bandwidth memory (HBM) chip stacking technologies face challenges with increasing parasitic parameters due to fringing field radiation and signal crosstalk, which affect bandwidth and power consumption, especially as integration levels increase.
Innovation Solution
A semiconductor structure and manufacturing method that includes a chip stack with conductive structures featuring concave and convex faces for reduced parasitic parameters, and through-silicon vias connected to conductive bumps, optimizing the arrangement to minimize fringing fields and enhance bonding quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip stacking height is increased to achieve higher integration, then bandwidth and power consumption are improved, but parasitic parameters (inductance, capacitance, resistance) increase due to fringing field radiation and signal crosstalk
Solution Approach 1:
The chip structure is divided into first and second sub-portions with different heights, creating a segmented architecture where the first sub-portion (with protruding second surface) and second sub-portion work together to reduce fringing field radiation. This segmentation allows the conductive structures to be optimally positioned to minimize parasitic effects while maintaining high integration benefits
Solution Approach 2:
The patent employs asymmetric chip structure where the first sub-portion has a protruding second surface relative to the second sub-portion. This asymmetric design creates optimized spacing and positioning for conductive structures, reducing signal crosstalk and fringing field radiation while enabling higher stacking density for improved bandwidth
2Loss of energy
If chip stacking height is increased to achieve higher integration, then power consumption is reduced, but parasitic parameters (inductance, capacitance, resistance) increase due to fringing field radiation and signal crosstalk
Solution Approach 1:
The segmented chip structure with first and second sub-portions enables optimized conductive structure placement that reduces parasitic inductance and resistance. This segmentation allows shorter current paths and better signal routing, reducing power loss while maintaining the energy efficiency benefits of high-density stacking
Solution Approach 2:
The patent utilizes vertical dimensionality with chips stacked in the thickness direction, creating a three-dimensional architecture. The asymmetric height design in the vertical dimension allows conductive structures to be positioned at optimized heights, reducing parasitic effects and power consumption simultaneously through spatial optimization
3Reliability
If conductive structures are added for electrical connection between chips, then signal integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The conductive bump and through-silicon via are merged into a single integrated conductive structure that performs both electrical connection and mechanical bonding functions. This merging simplifies the manufacturing process by reducing the number of separate components and assembly steps while maintaining excellent signal integrity through the continuous conductive path
Data Source
AI summary
A semiconductor structure includes a base, a chip stack located on the base, and first conductive structures. The chip stack includes chips stacked in sequence in a direction perpendicular to a plane of the base, a chip includes first and second sub-portions, a first surface of the first sub-portion is flush with that of the second sub-portion, a second surface of the first sub-portion protrudes from that of the second sub-portion, and the first and second surfaces are oppositely arranged. A first conductive structure includes a first conductive bump and a first through-silicon via, the first conductive bump is located between first sub-portions of two adjacent chips, the first through-silicon via penetrates through the first sub-portion in the direction perpendicular to the plane of the base and is connected to the first conductive bump, and the materials of the first conductive bump and the first through-silicon via are same.