HBM Die-Interposer Layout for High Bandwidth With Lower Power
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Solution Overview
Problem
There is a need for systems and methods that improve efficient power usage in electronic devices as the size of electronics decreases and the amount of heat generated by components increases.
Innovation Solution
The described systems and methods involve configuring high bandwidth memory configurations by positioning a first memory physical layer (PHY) interface on a compute die, connecting memories via through-silicon via (TSV) connections, and positioning compute and base dies on a silicon interposer to maximize memory channels and reduce power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory capacity and bandwidth are increased to handle rapidly growing data amounts, then data processing capability is improved, but power consumption and heat generation increase
Solution Approach 1:
The patent transitions from traditional 2D memory arrangement to 3D stacked memory architecture, where multiple memory dies are vertically stacked and connected via through-silicon vias (TSVs). This vertical stacking increases memory capacity and bandwidth without proportionally increasing the footprint area, thereby improving data processing capability while controlling power consumption per unit area.
Solution Approach 2:
The patent introduces a silicon interposer as an intermediary substrate that hosts memory PHY interfaces and facilitates high-speed connections between compute dies and stacked memory modules. The interposer acts as a mediator that enables efficient data transfer between the compute unit and memory stacks, optimizing power usage by reducing transmission distances and improving signal integrity.
2Volume of moving object
If device size is decreased to improve portability, then device compactness is improved, but heat dissipation becomes more difficult
Solution Approach 1:
By stacking memory dies vertically in the Z-dimension rather than expanding horizontally in the X-Y plane, the patent achieves high memory capacity within a smaller footprint. This 3D integration allows compact device design while distributing heat generation across multiple vertical layers, improving thermal management in space-constrained environments.
Solution Approach 2:
The patent divides the memory system into multiple separate dies stacked vertically, each generating heat independently. This segmentation distributes thermal load across different spatial locations and time periods, preventing concentrated heat buildup that would occur in a monolithic structure, thereby facilitating better heat dissipation in compact devices.
3Speed
If memory bandwidth is increased to improve data access speed, then data transfer rate is improved, but memory access latency may increase due to complex routing
Solution Approach 1:
The silicon interposer provides dedicated high-speed interconnects and memory PHY interfaces that directly bridge compute dies and memory stacks. This intermediary architecture creates optimized data pathways with minimal routing complexity, enabling high bandwidth data transfer while maintaining low latency through direct physical connections and specialized interface circuits.
Solution Approach 2:
The vertical stacking architecture with TSV connections creates direct short-path routes between memory layers and the interposer, reducing the number of interconnection hops compared to lateral routing. This 3D arrangement minimizes signal propagation distance and routing complexity, achieving high data transfer rates with reduced access latency.
Data Source
AI summary
Provided are systems, methods, and apparatuses for high bandwidth memory configurations. In one or more examples, the systems, devices, and methods include positioning a first memory physical layer (PHY) interface on a surface of a compute die and connecting a first memory to the first memory PHY interface of the compute die via a first through-silicon via (TSV) connection. The systems, devices, and methods include connecting a second memory to a base die that connects to the compute die via a silicon interposer, positioning the compute die on the silicon interposer, and positioning the base die on the silicon interposer.