Direct Access Hybrid Testing for HBM Memory Devices

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Solution Overview

Problem

It is challenging to perform tests on memory devices packaged in system-in-package (SiP) devices using long test patterns due to the limited number of direct access terminals, which are inefficient for transmitting extensive data required for thorough testing.

Innovation Solution

The implementation of a direct access hybrid testing method that pre-loads test patterns into a memory device's look-up table, using direct access terminals to provide test instructions and retrieve patterns for writing and comparing data, with an error catch memory circuit to generate result information, allowing for efficient testing without relying on the host device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If long test patterns are provided through direct access terminals, then testing thoroughness is improved, but terminal availability and efficiency deteriorate due to limited number of terminals

Engineering Contradiction:
Improvetesting thoroughnessVSAvoidterminal efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the test data into two parts: test instructions (provided through direct access terminals) and test patterns (pre-loaded into the memory device). This segmentation allows the limited direct access terminals to focus on transmitting control instructions while the bulk data patterns are stored locally, resolving the contradiction between testing thoroughness and terminal efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-loading test patterns into the memory device's look-up table before the actual testing process. This preparation step enables the memory device to have immediate access to extensive test patterns without requiring continuous data transmission through the limited direct access terminals during testing, thereby improving both testing thoroughness and terminal efficiency

Inventive Principle:
Principle #10Preliminary action

2Speed

If direct access terminals are used for testing, then access speed is improved by bypassing host device, but data transmission capability deteriorates due to limited terminal count

Engineering Contradiction:
Improveaccess speedVSAvoiddata transmission capability
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent introduces a new dimension of data storage by utilizing the memory device's internal look-up table capacity. Instead of relying solely on the direct access terminals for data transmission, the system leverages the memory device's inherent storage capability to hold test patterns, effectively adding a spatial dimension for data accommodation that bypasses the terminal count limitation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The look-up table acts as an intermediary between the direct access terminals and the memory array. It receives test instructions from the terminals and provides the corresponding pre-stored test patterns, mediating the data flow so that minimal data needs to be transmitted through the limited terminals while still enabling comprehensive testing

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11581056B2Apparatuses and methods for direct access hybrid testing
Publication Date: 2023.02.14 MICRON TECHNOLOGY INC
  • US11581056B2 patent drawing
  • US11581056B2 patent drawing
  • US11581056B2 patent drawing

AI summary

Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.