HBM Stack Side-Edge Interconnect for TSV-Free Thermal Management
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Solution Overview
Problem
Existing 2.5D/3D ICs face challenges in power, performance, area, and cost optimization due to bottom/top electrical interconnects, and insufficient heat dissipation from stacked DRAM memory semiconductor dies, leading to elevated chip temperatures.
Innovation Solution
A memory stack design with edge pads and high thermal conductivity layers between semiconductor dies, eliminating through-silicon vias and interposers, and utilizing high thermal conductivity materials like SiC, AlN, BN, W, or copper to enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) and interposers are used for electrical interconnection in stacked memory structures, then electrical connectivity between dies is achieved, but manufacturing complexity and alignment difficulty increase significantly
Solution Approach 1:
The patent removes the interposer layer entirely from the stacked memory structure, eliminating the need for TSVs in the interposer and simplifying the overall manufacturing process while maintaining electrical connectivity through direct die-to-die bonding interfaces
Solution Approach 2:
The patent divides the electrical interconnection function into separate bonding interfaces between individual dies, allowing each die to be manufactured and tested independently before stacking, thereby reducing alignment complexity and manufacturing difficulty
2Productivity
If multiple DRAM memory semiconductor dies are stacked vertically to increase capacity, then integration density improves, but heat dissipation capability deteriorates causing elevated chip temperatures
Solution Approach 1:
The patent transitions from purely vertical heat dissipation paths to include lateral heat dissipation pathways by incorporating heat spreaders that extend laterally and thermal vias that provide multiple-dimensional heat conduction routes, effectively managing heat in stacked high-density memory structures
Solution Approach 2:
The patent introduces heat spreaders and thermal interface materials as intermediary layers between stacked memory dies, which act as thermal conduits to efficiently conduct heat away from the stacked dies to external heat sinks, thereby maintaining operational temperatures
3Reliability
If bottom/top electrical interconnects are used in packaged structures, then electrical connection is established, but power, performance, area and cost optimization becomes severely constrained
Solution Approach 1:
The patent enables flexible design optimization by allowing dynamic selection of bonding interface configurations, interconnect patterns, and stacking arrangements, giving designers adaptability to optimize for different power, performance, area and cost requirements without being constrained by fixed bottom/top interconnect geometries
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved heat dissipation and reduced chip temperatures, optimizing power, performance, and cost by eliminating interconnect constraints and enhancing thermal conductivity.
Implementation Method 1
utilizing high thermal conductivity materials like SiC, AlN, BN, W, or copper to enhance heat dissipation
Data Source
AI summary
An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.