HBM Stack Side-Edge Interconnects for TSV-Free Thermal Control
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Solution Overview
Problem
Existing 2.5D/3D ICs face challenges in power, performance, area, and cost optimization due to bottom/top electrical interconnects, and insufficient heat dissipation from stacked DRAM memory semiconductor dies, leading to elevated chip temperatures.
Innovation Solution
A novel IC structure with a memory stack comprising semiconductor dies separated by high thermal conductivity layers, eliminating interposers and TSVs, and utilizing edge pads for interconnects, along with a logic die and packaging substrate, enhancing thermal management through high thermal conductivity materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) are used for electrical interconnects in stacked memory dies, then vertical electrical connection is achieved, but manufacturing complexity and alignment difficulty increase severely
Solution Approach 1:
The patent extracts the TSV formation process from the manufacturing flow by using dies with pre-formed edge pads that eliminate the need for TSVs. The electrical interconnection is achieved through edge pad bonding rather than through-silicon via formation, removing the complex TSV alignment and formation steps from the manufacturing process.
Solution Approach 2:
Instead of forming vertical connections through the bulk of the silicon die (TSVs), the patent inverts the approach by using edge pads located at the periphery of the die surfaces. This peripheral interconnection approach replaces the conventional central TSV architecture, simplifying the manufacturing process while achieving the same electrical interconnection function.
2Productivity
If multiple DRAM memory semiconductor dies are stacked vertically, then integration density increases, but heat dissipation capability deteriorates leading to elevated chip temperatures
Solution Approach 1:
The patent transitions from purely vertical heat dissipation pathways to include lateral heat dissipation pathways by positioning heat sinks at the side edges of the stacked memory module. This multi-dimensional heat dissipation approach (combining vertical and lateral paths) effectively manages thermal loads from high-density stacked dies without requiring increased vertical spacing.
Solution Approach 2:
The patent introduces thermal interface materials and heat dissipation structures as intermediary elements between the stacked memory dies and the external environment. These intermediaries (thermal interface materials, heat sinks) facilitate efficient heat transfer from the high-density die stack to the surrounding cooling structures, managing thermal accumulation in the compact vertical arrangement.
3Reliability
If bottom/top electrical interconnects are used in 2.5D/3D IC packaging, then electrical connection is established, but power, performance, area, and cost optimization becomes constrained
Solution Approach 1:
The patent segments the electrical interconnection function into multiple edge pad locations around the periphery of each die. Instead of relying on a single bottom or top interconnect interface, the edge pads distributed around the die perimeter provide multiple connection points, enabling greater design flexibility in routing and interconnection schemes while maintaining reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves thermal dissipation and reduces chip temperature, optimizing power and performance while maintaining a compact design, thereby addressing the limitations of conventional 2.5D/3D ICs.
Implementation Method 1
A novel IC structure with a memory stack comprising semiconductor dies separated by high thermal conductivity layers
Data Source
AI summary
An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.