HBM Memory Stack Hybrid Bonding for Lower Routing Latency
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Solution Overview
Problem
High-Performance Computing (HPC) systems face challenges in reducing latency and improving operation speed due to the distance between memory and logic dies in current High-Bandwidth-Memory (HBM) stacks, where memory dies are stacked with solder bonding or metal direct bonding through micro bumps, leading to increased electrical routing distances.
Innovation Solution
The solution involves bonding a peripheral device to a memory device using hybrid bonding techniques, where the peripheral device and memory device are formed on separate substrates using different technologies, such as CMOS and DRAM processes, to reduce the electrical routing distance and improve latency by forming a memory structure with a hybrid bond that includes Si—O—Si bonds and direct metal-to-metal bonds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are stacked with solder bonding or metal direct bonding through micro bumps, then memory capacity is increased, but electrical routing distance increases leading to higher latency
Solution Approach 1:
The patent transitions from vertical stacking (3D stacking) to lateral integration by bonding the peripheral device to the side surface of the memory die. This dimensional change allows electrical connections to be established in the lateral direction rather than requiring signals to traverse through multiple stacked layers, thereby reducing routing distance and latency while maintaining high memory capacity through the stacked configuration.
Solution Approach 2:
The peripheral device acts as an intermediary component that provides alternative electrical connection paths. By bonding this peripheral device to the side surface of the memory die, the patent creates intermediate connection points that shorten the electrical routing distance between memory components and external interfaces, reducing the time delay associated with signal traversal through the stacked structure.
2Loss of time
If memory dies are stacked closer together, then latency is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the system into separate functional modules: memory dies stacked for capacity and a peripheral device bonded to the side surface for optimized electrical connections. This segmentation allows each module to be manufactured and optimized independently, with the memory dies maintaining standard stacking procedures while the peripheral device provides lateral connectivity, thereby reducing overall manufacturing complexity compared to reconfiguring the entire stacked structure.
3Adaptability or versatility
If different technologies are used for peripheral device and memory device, then design flexibility is improved, but bonding complexity increases
Solution Approach 1:
The patent employs hybrid bonding techniques that create standardized interface patterns on both the memory die and peripheral device surfaces. These standardized patterns act as templates that facilitate alignment and bonding between different technology nodes, allowing CMOS and DRAM processes to be integrated despite their differences. The standardized interface copying enables automated bonding processes, reducing the complexity that would otherwise arise from customizing connections for each technology combination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces latency and enhances high-speed operation by minimizing the electrical routing distance between the peripheral device circuitry and memory components, allowing for flexible design configurations and optimized performance through the use of different technologies for each device.
Implementation Method 1
bonding the peripheral device to the memory device using hybrid bonding techniques... to form a hybrid bond that includes Si—O—Si bonds and direct metal-to-metal bonds
Data Source
AI summary
A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.