HBM Interface Latency Counter for Implicit Precharge
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Solution Overview
Problem
In High Bandwidth Memory (HBM) systems, implementing implicit precharge operations requires a latency counter that increases current consumption when placed on memory core chips, as it necessitates a clock signal from the interface chip, leading to inefficiencies.
Innovation Solution
The latency counter is placed on the interface chip, generating internal commands after a predetermined clock cycle, eliminating the need for a clock signal to be supplied to memory core chips and reducing current consumption, while the state circuit determining active states is distributed across memory core chips, eliminating the need for its presence on the interface chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the latency counter is placed on the memory core chips to enable implicit precharge operations, then the implicit precharge function is achieved, but current consumption increases due to the need for clock signal supply from the interface chip
Solution Approach 1:
The patent segments the implicit precharge functionality by separating the latency counter from the memory core chips and placing it on the interface chip. This segmentation allows the memory core chips to perform implicit precharge operations without requiring their own dedicated latency counters, thereby reducing their current consumption while maintaining the functionality.
Solution Approach 2:
The interface chip's latency counter serves multiple purposes: it generates internal commands for implicit precharge operations across multiple memory core chips simultaneously. This multi-functional approach allows a single latency counter on the interface chip to control precharge operations for several memory banks across different core chips, eliminating the need for separate counters on each core chip.
2Adaptability or versatility
If the latency counter is placed on the memory core chips, then implicit precharge operations can be performed, but the system complexity increases due to the need for clock signal transmission from the interface chip to memory core chips
Solution Approach 1:
The patent extracts the latency counter functionality from the memory core chips and relocates it to the interface chip. This extraction eliminates the need for clock signal transmission infrastructure between the interface chip and memory core chips, as the latency counter now resides on the interface chip where the clock signal already originates.
Solution Approach 2:
The patent merges the latency counter functionality into the interface chip, combining the command generation and timing control functions in a single location. This consolidation eliminates the need for separate latency counters on each memory core chip and the associated clock signal distribution infrastructure, thereby reducing system complexity.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.