Local Cache Array for HBM DRAM Row Activation Reduction
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Solution Overview
Problem
Current memory systems face performance bottlenecks and high power consumption due to low page hit rates in HBM DRAM and the row activate cycle limitations, which can lead to page trashing and increased thermal challenges.
Innovation Solution
Implementing a local cache array with a row cache technology that allows for independent read and write access without activating a DRAM row, using a per-bank row cache size that is an integer multiple of the DRAM page size, and utilizing cache commands to fetch additional cachelines into the row cache based on hints in read commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If row activate cycle is used for DRAM access, then data can be read from memory cells, but access time and power consumption increase due to frequent row activations
Solution Approach 1:
The patent implements a row cache that pre-loads and stores recently accessed DRAM rows before they are needed. When data is requested, the row cache checks if the required row is already cached, eliminating the need for immediate row activation. This preliminary action of caching frequently accessed rows reduces both access time and power consumption by avoiding repeated row activation cycles.
Solution Approach 2:
The patent introduces a row cache as an intermediary layer between the memory controller and the DRAM array. This intermediary structure holds copies of frequently accessed rows, allowing the system to service read requests from the cache without activating the actual DRAM rows. The row cache acts as a buffer that mediates between the high-speed access requirements and the power-consuming DRAM row activation process.
2Productivity
If HBM DRAM is used for high bandwidth, then data transfer rate increases, but page hit rate decreases leading to page trashing
Solution Approach 1:
The patent segments the memory system into multiple independent row caches, each associated with specific DRAM banks. This segmentation allows different cache structures to be optimized for different access patterns. By dividing the cache into multiple segments that can independently manage their own cached rows, the system improves page hit rates without compromising the high bandwidth capability of the HBM DRAM architecture.
3Use of energy by stationary object
If row cache is implemented to reduce access time, then power consumption decreases, but device complexity increases
Solution Approach 1:
The patent implements row caches with different sizes and configurations for different DRAM banks based on their specific access patterns and performance requirements. Rather than using a uniform cache structure throughout the system, each bank can have a row cache optimized for its local characteristics. This local quality approach reduces overall device complexity by allowing selective optimization rather than requiring a complex unified cache structure.
Data Source
AI summary
An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.