Intermediary IC Connection for HBM Speed and Logic Die Bottlenecks
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Solution Overview
Problem
The existing technologies face challenges in optimizing the interface between High Bandwidth Memory (HBM) and logic dies, leading to bottlenecks that limit the overall system performance, particularly in applications demanding high-speed data processing like artificial intelligence and real-time graphics rendering.
Innovation Solution
The introduction of a droplet chip or droplet circuit that acts as an intermediary between HBM and processing units, bypassing the data rate limitations of the logic die and enabling high-speed data transfers while reducing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If HBM operates at high speed, then data transfer rate is improved, but power consumption increases
Solution Approach 1:
The intermediary circuit implements periodic data transfer operations, buffering high-speed data from HBM and transferring it to the logic die in controlled bursts at the logic die's maximum processing rate. This periodic action allows the system to maintain high data transfer rates from HBM while managing power consumption by matching the logic die's processing capacity, avoiding continuous high-power operation.
2Quantity of substance
If HBM is connected to logic die, then memory capacity is improved, but latency increases
Solution Approach 1:
The intermediary circuit performs preliminary buffering and pre-processing of data from HBM before transferring it to the logic die. By preparing data in advance in high-speed buffers and organizing it for optimal processing, the system reduces latency when data reaches the logic die, thus maintaining both high memory capacity and low latency performance.
Data Source
AI summary
The subject technology is directed to integrated circuit technologies. In an embodiment, the subject technology provides a device that comprises a first circuit and a second circuit and a third circuit. The first circuit is coupled to the second circuit and the third circuit through a first interconnect. The third circuit is coupled to a fourth circuit through a second interconnect. The fourth circuit includes a processor circuit. The third circuit may support data transfer at a speed greater than what the second circuit could handle, facilitating the data transmission between the first circuit and the fourth circuit. There are other embodiments as well.