HBM Logic Die IO Layout for Shorter 2×2 Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IC designs face challenges in implementing three HBM logic dies per compute die within a 2×2 matrix due to alignment issues and increased interconnect lengths, leading to performance degradation and cost inefficiencies.
Innovation Solution
Implement HBM logic dies with additional IO ports and utilize controller circuitry to selectively couple these ports with compute dies, allowing for flexible alignment configurations that maintain linear interconnects and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If HBM logic dies are aligned with compute dies in a 2×2 matrix, then integration density is improved, but interconnect length increases causing performance degradation
Solution Approach 1:
The HBM logic die is designed with an asymmetric layout where the IO port is positioned at a corner rather than centered. This asymmetric positioning allows the HBM logic die to be placed in corner positions of the 2×2 matrix, creating shorter interconnect paths to adjacent compute dies while maintaining proper electrical connections.
Solution Approach 2:
The patent transitions from traditional centered alignment to corner-based positioning in the spatial arrangement of dies. By utilizing the corner positions and asymmetric IO port placement, the interconnect paths are optimized in the two-dimensional die array, reducing the effective connection length between HBM logic and compute units.
2Adaptability or versatility
If additional IO ports are added to HBM logic dies, then alignment flexibility is improved, but device complexity increases
Solution Approach 1:
The HBM logic die incorporates multiple IO ports that can serve different alignment configurations. The same die design with additional IO ports can accommodate various positions in the 2×2 matrix (corner, edge, or center positions), providing universal adaptability across different system layouts without requiring multiple specialized die designs.
3Productivity
If three HBM logic dies are integrated per compute die, then bandwidth is maximized, but manufacturing cost increases
Solution Approach 1:
The system is segmented into discrete HBM logic dies that can be independently fabricated and then integrated with compute dies. This segmentation allows standardization of the HBM logic die design, enabling economies of scale in manufacturing and reducing per-unit costs when integrating multiple HBM logic dies with each compute die.
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods to implement a High Bandwidth Memory (HBM) are disclosed. An example method includes identifying, with memory controller circuitry, a first input output (IO) port on the memory controller circuitry that is coupled to programmable circuitry, identifying, with the memory controller circuitry, a second IO port on the memory controller circuitry that is disconnected from the programmable circuitry, identifying a third IO port on the memory controller circuitry that is coupled to the programmable circuitry, and using, with the memory controller circuitry, one or more of the first and third IO ports to communicate with the programmable circuitry.