HBM Storage Module Layout for Uniform Chip Communication Delays
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Solution Overview
Problem
As the number of stacked layers in High Bandwidth Memory (HBM) increases, there is a significant difference in communication distances between storage chips and logic chips, leading to varying communication delays and performance issues, which affect the running speed and stability of the semiconductor structure.
Innovation Solution
The storage chips are stacked in a direction parallel to the bottom surface of a substrate with a groove, and a power supply wiring layer is electrically connected to power supply signal lines and pins through conductive parts, ensuring uniform communication delays and reliable power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage chips are stacked in vertical direction perpendicular to substrate surface, then storage capacity and integration level are improved, but communication delay difference between stacked chips and logic chip increases
Solution Approach 1:
The patent changes the stacking direction from vertical (perpendicular to substrate) to horizontal (parallel to substrate bottom surface), utilizing the groove structure to accommodate chips in a different spatial dimension. This dimensional change maintains high integration while equalizing communication distances to all logic chips on the substrate surface.
Solution Approach 2:
The groove structure acts as an intermediary element that enables horizontal stacking of storage chips while maintaining their positional relationship with logic chips. The groove provides a dedicated space that facilitates uniform communication paths without requiring complex routing adjustments.
2Quantity of substance
If multiple storage chips are stacked to increase density, then storage capacity is improved, but power supply complexity and packaging difficulty increase
Solution Approach 1:
The patent merges the power supply wiring layer with the storage chip structure itself, where the wiring layer is formed on the storage chip and extends to the groove sidewall. This integration simplifies the overall power supply system by eliminating separate power delivery structures and reducing packaging complexity.
Solution Approach 2:
The storage chip's own wiring layer serves dual purposes: internal chip interconnection and external power supply connection to the substrate. The wiring layer extends naturally from the chip to the groove sidewall, providing self-contained power delivery without requiring additional external wiring structures.
3Quantity of substance
If storage chips are stacked vertically to achieve high bandwidth, then storage capacity is improved, but manufacturing precision requirements increase due to alignment difficulties
Solution Approach 1:
By transitioning from vertical stacking to horizontal stacking within the groove, the patent eliminates the need for precise vertical alignment between multiple chip layers. The groove structure provides natural lateral positioning, significantly reducing manufacturing precision requirements while maintaining high storage capacity.
Data Source
AI summary
A semiconductor structure, a method for manufacturing same, and a semiconductor device are provided. The semiconductor structure includes: a substrate having a groove and power supply pins; a storage module located in the groove; in which the storage module includes a plurality of storage chips stacked in a first direction, the first direction being parallel to the bottom surface of the groove; power supply signal lines being provided in each of the storage chips, and at least one of the plurality of storage chips having a power supply wiring layer electrically connected to the power supply signal lines; and conductive parts connected with the power supply wiring layer and the power supply pins.