HBM Semiconductor Package Structure With Two-Stage Base Plates
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Solution Overview
Problem
As the number of stacking layers in High Bandwidth Memory (HBM) increases, communication latency and voltage drop issues arise due to longer distances between DRAM dies and logic dies, leading to instability and reduced performance.
Innovation Solution
A semiconductor package structure is designed with a first base plate connected to both a first semiconductor chip and a second semiconductor chip stacking structure, where the second chip stacking structure is powered through a two-stage base plate configuration, reducing voltage drop and enhancing communication efficiency by using conductive bumps and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacking layers in HBM is increased, then the memory capacity and bandwidth are improved, but the communication latency and voltage drop increase
Solution Approach 1:
The patent divides the single long power supply link into multiple shorter links by introducing intermediate base plates at different stacking layers. Each base plate independently powers the DRAM dies at its level, segmenting the power distribution system to reduce cumulative voltage drop and improve power delivery reliability.
Solution Approach 2:
The patent transitions from a single-layer base plate architecture to a multi-layer base plate architecture, adding the vertical dimension of power distribution. This allows power to be delivered from multiple levels, reducing the effective length of each power link and improving overall system reliability.
2Quantity of substance
If the number of stacking layers in HBM is increased, then the memory capacity is improved, but the voltage drop increases
Solution Approach 1:
The power supply path is segmented into multiple shorter segments by introducing intermediate base plates. Each segment delivers power over a shorter distance, reducing the cumulative voltage drop that would occur in a single long link from the bottom base plate to the top DRAM dies.
Solution Approach 2:
Intermediate base plates act as mediator structures that receive power from the bottom base plate and independently power the DRAM dies at their respective levels. This intermediary power distribution reduces the voltage drop by breaking the direct long-path dependency.
3Device complexity
If the number of stacking layers in HBM is increased, then the integration level is improved, but the communication latency increases
Solution Approach 1:
The patent segments the monolithic stacked structure into modular layers with independent base plates. This segmentation allows for shorter communication paths between logic and memory at each level, reducing latency while maintaining high integration through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively shortens the power supply link, reduces voltage drop, and improves communication reliability between stacked semiconductor chips, addressing the challenges of increased layer counts in HBM technology.
Implementation Method 1
A plurality of second conductive bumps are formed on a side of each of the first chip stacking structure and the second chip stacking structure that are away from each other in the first direction. A signal line in each of the plurality of second base plates is connected to the plurality of second conductive bumps.
Data Source
AI summary
A semiconductor package structure includes: a first base plate; a first semiconductor chip connected to the first base plate; a second semiconductor chip stacking structure including at least one first chip stacking structure and at least one second chip stacking structure; and a plurality of second base plates. The first and second chip stacking structures are arranged side-by-side on the first semiconductor chip in a first direction, a plurality of second conductive bumps are formed on sides of the first and second chip stacking structure that is away from each other in the first direction, the first direction being parallel to a plane where the first base plate is located. A signal line in each second base plate is connected to the second conductive bumps. The second base plates are connected to the first base plate in a direction perpendicular to the plane where the first base plate is located.