HBM Package Structure With Buffer Cap to Reduce Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges in further miniaturization and increased integration density due to limitations in packaging techniques for semiconductor dies, particularly in achieving higher bandwidth, lower power consumption, and reduced latency, which existing methods struggle to address effectively.
Innovation Solution
The development of high bandwidth memory (HBM) devices involves stacking semiconductor wafers with memory dies and conductive terminals, using a gap filling material for pre-bonding, and a single bonding process to form solder joints, along with an insulating encapsulation and buffer material layers to enhance reliability and reduce joint failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor wafers are stacked to increase integration density, then the physical size is reduced, but manufacturing complexity and reliability challenges increase
Solution Approach 1:
The manufacturing process is divided into distinct stages: pre-bonding stage using gap filling material, and final bonding stage using solder material. This segmentation allows each stage to be optimized independently, reducing overall manufacturing complexity while enabling 3D stacking.
Solution Approach 2:
Gap filling material is applied before the final bonding process to pre-position and stabilize the stacked wafers. This preliminary action reduces warpage and alignment issues during subsequent soldering, simplifying the overall manufacturing process.
2Quantity of substance
If multiple semiconductor wafers are stacked, then integration density increases, but warpage and joint failure risk increase
Solution Approach 1:
Gap filling material is applied between stacked wafers before final soldering to cushion and absorb thermal expansion differences and mechanical stress. This prevents warpage and reduces the risk of joint failure during the bonding process and operation.
Solution Approach 2:
The gap filling material acts as an intermediary layer between stacked wafers, mediating thermal and mechanical stresses. This intermediary layer protects the solder joints from excessive stress, reducing joint failure risk while enabling higher integration density.
3Ease of manufacture
If conventional packaging techniques are used, then manufacturing is simpler, but bandwidth and power consumption requirements cannot be met
Solution Approach 1:
The patent transitions from conventional 2D packaging to 3D stacking architecture. By adding the vertical dimension with multiple stacked wafers connected through solder joints, bandwidth is significantly increased while maintaining manufacturing feasibility through the pre-bonding gap filling technique.
4Manufacturing precision
If minimum feature size is reduced, then integration density improves, but packaging technique limitations become more significant
Solution Approach 1:
The packaging process is segmented into pre-bonding (gap filling) and final bonding (soldering) stages. This segmentation allows precise control at each stage, accommodating reduced minimum feature sizes without proportionally increasing overall packaging complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-performance HBM devices with improved reliability and reduced warpage, addressing the need for smaller form factors and higher bandwidth while ensuring mechanical and electrical connectivity between stacked memory dies.
Implementation Method 1
a single bonding process to form solder joints
Data Source
AI summary
A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.