HBM Semiconductor Package Structure for Shorter Chip Communication Paths
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Solution Overview
Problem
As the number of stacked layers in High Bandwidth Memory (HBM) technology increases, communication delays and voltage drop issues arise due to longer distances between DRAM chips and logic dies, leading to technical difficulties in maintaining efficient data transfer and power supply.
Innovation Solution
A semiconductor package structure is developed with a first semiconductor chip connected to a base and a second semiconductor chip stack structure arranged in a parallel and vertical stack configuration, allowing wireless communication between chips and connecting to a second base via leads, which reduces communication difficulties and voltage drop problems by using conductive bumps for power supply and signal exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked layers in HBM is increased to improve bandwidth and computing power, then the I/O bottleneck is reduced, but communication delays and voltage drop issues arise due to longer distances between DRAM chips and logic dies
Solution Approach 1:
The patent transitions from traditional horizontal interconnection to vertical stacking architecture, moving components into the third dimension. Multiple DRAM chip stacks are arranged vertically above the logic die, with interconnections extending through the vertical dimension via TSVs. This dimensional change increases bandwidth by adding more memory capacity without proportionally increasing communication distance, as all stacks connect to the same logic die plane.
Solution Approach 2:
The patent introduces intermediate connection structures including TSVs (through-silicon vias), redistribution layers (RDL), and buffer chips that act as mediators between the DRAM stacks and logic die. These intermediaries manage the complex interconnections, distribute signals efficiently, and compensate for voltage drops by providing localized power redistribution and signal buffering across multiple stacking layers.
2Productivity
If the number of stacked layers in HBM is increased to improve bandwidth and computing power, then the I/O bottleneck is reduced, but voltage drop problems occur due to longer distances between DRAM chips and logic dies
Solution Approach 1:
The patent segments the power distribution system into multiple independent power delivery paths through separate TSV connections and power rails for each DRAM stack. Instead of a single long power path, each stack has dedicated power vias and redistribution layers that create short, localized power delivery loops. This segmentation reduces voltage drop by eliminating long series connection paths and providing multiple parallel power delivery routes.
Solution Approach 2:
The patent implements three-dimensional power distribution networks with vertical power vias and layered redistribution structures. Power is delivered through the vertical dimension using TSVs that penetrate multiple chip layers, creating direct vertical power paths from the logic die to each DRAM stack. This vertical power delivery architecture reduces the horizontal current path length, minimizing resistive voltage drops compared to traditional planar power distribution.
3Ease of manufacture
If traditional horizontal interconnection is used, then manufacturing is simpler, but bandwidth is limited by the number of chip pins
Solution Approach 1:
The patent employs vertical stacking with TSV interconnections to overcome pin count limitations. Instead of expanding the horizontal interconnect footprint, the architecture stacks multiple DRAM chips vertically above the logic die, with TSVs providing through-silicon vertical interconnections. This enables hundreds of memory bits to be connected to the logic die through a manageable number of vertical vias, achieving high bandwidth without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent implements nested interconnection structures where TSVs are formed within the silicon substrate, surrounded by conductive fill and insulation layers, which are then encapsulated by redistribution layers and additional TSV structures in upper layers. This nested architecture allows multiple interconnection levels to be integrated within the vertical space of each chip stack, enabling complex high-bandwidth connectivity while maintaining a compact footprint that simplifies packaging and assembly.
Data Source
AI summary
Provided are semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes: a first base; a first semiconductor chip connected to the first base; a second semiconductor chip stack structure located on the first semiconductor chip, the second semiconductor chip stack structure including a plurality of second semiconductor chips stacked in sequence in a first direction, the second semiconductor chip stack structure being provided with a plurality of first leads on an outermost side of the second semiconductor chips in the first direction, in which the first direction is a direction parallel to a plane of the first base; and at least one second base, signal lines in the at least one second base being connected to the first leads, the at least one second base being connected to the first base in a direction perpendicular to the plane of the first base.