HBM Package Structure With Side Bumps to Cut Die Communication Delay
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Solution Overview
Problem
The increasing integration level of High Bandwidth Memory (HBM) technology leads to challenges in communication delays and area sacrifices due to the increasing number of stacked DRAM dies, which complicates the packaging process and reduces reliability.
Innovation Solution
A semiconductor package structure is developed with a first substrate, a first semiconductor die, a second semiconductor die stack structure with multiple dies stacked in a side-by-side and vertical manner, and a second substrate connected to the first substrate, allowing wireless communication between dies and reducing the need for through silicon vias, thus enhancing communication efficiency and mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked DRAM dies is increased to improve integration level and bandwidth, then memory capacity and bandwidth are improved, but communication delay increases and packaging complexity increases
Solution Approach 1:
The patent transitions from traditional vertical stacking to a three-dimensional arrangement where DRAM dies are stacked vertically and logic dies are arranged horizontally in parallel. This multi-dimensional layout reduces communication distance between stacked DRAM dies and logic units, thereby reducing communication delay while maintaining high integration level and bandwidth.
Solution Approach 2:
The patent divides the semiconductor package into separate functional modules: DRAM die stacks and logic die stacks, which are independently formed and then integrated. This segmentation allows for optimized communication paths between modules, reducing overall communication delay while maintaining high bandwidth through parallel data transfer channels.
2Productivity
If the number of stacked DRAM dies is increased to improve integration level, then memory capacity is improved, but packaging process complexity increases
Solution Approach 1:
The patent divides the complex packaging process into separate stages: first forming DRAM die stacks independently, then forming logic die stacks separately, and finally integrating them through wire bonding. This segmentation of the packaging process reduces overall complexity by allowing each stage to be optimized independently.
Solution Approach 2:
The patent performs preliminary actions by pre-forming DRAM die stacks and logic die stacks as separate modules before final integration. This preliminary stacking and testing of individual modules simplifies the final packaging process and reduces the complexity of handling multiple individual dies.
3Ease of operation
If traditional vertical stacking with through silicon vias is used, then communication between dies is achieved, but mechanical strength is reduced and manufacturing complexity increases
Solution Approach 1:
The patent replaces the mechanical through silicon via system with a wire bonding system for inter-die communication. Wire bonding provides better mechanical strength to the stacked dies while achieving the same communication function, thereby resolving the contradiction between communication capability and mechanical strength.
Data Source
AI summary
A semiconductor package structure includes: a first substrate; a first semiconductor die connected to the first substrate; a second semiconductor die stack structure located on the first semiconductor die, the second semiconductor die stack structure includes a plurality of second semiconductor dies sequentially stacked onto one another in a first direction, a plurality of second conductive bumps being formed on a side of the second semiconductor die stack structure in the first direction, in which the first direction is a direction parallel to a plane where the first substrate is located; and a second substrate, a signal line in the second substrate being connected to the plurality of second conductive bumps, the second substrate being connected to the first substrate in a direction perpendicular to the plane where the first substrate is located.