HBM Package Structure With Single-Step Die Bonding
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller, faster, and more energy-efficient semiconductor devices due to limitations in packaging techniques, particularly for stacked semiconductor devices like 3DICs, which require innovative methods to reduce form factor and enhance reliability.
Innovation Solution
The development of high bandwidth memory (HBM) devices involves a method of stacking memory dies over a semiconductor wafer, using a gap filling material to pre-bond the dies and a single bonding process to form solder joints, followed by encapsulation and singulation to create reliable package structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple bonding processes are used to stack memory dies, then reliable solder joints can be formed, but the manufacturing process becomes complex and time-consuming
Solution Approach 1:
The patent combines multiple bonding operations into a single bonding process. Specifically, the first memory die and second memory die are both bonded to the base semiconductor die in one continuous bonding operation, rather than performing separate bonding processes for each die. This merging approach maintains solder joint reliability while significantly reducing process complexity and manufacturing time.
Solution Approach 2:
The patent employs preliminary positioning and alignment of memory dies on the base semiconductor die before the bonding process. The dies are pre-configured in their final stacked positions with proper alignment, so that when the single bonding process is executed, all solder joints are formed correctly in one operation. This preliminary preparation enables the single bonding process to achieve what would otherwise require multiple iterative bonding steps.
2Ease of manufacture
If conventional packaging techniques are used, then manufacturing is straightforward, but the form factor and performance requirements for modern semiconductor devices cannot be met
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to three-dimensional stacked packaging. Multiple memory dies are vertically stacked above the base semiconductor die, utilizing the vertical dimension to increase integration density. This dimensional change dramatically reduces the lateral form factor of the device while maintaining manufacturing feasibility through automated pick-and-place and bonding processes.
Solution Approach 2:
The patent implements a nested structure where memory dies are stacked vertically, with each die positioned on top of the previous one, similar to nested dolls. The first memory die is bonded to the base semiconductor die, and the second memory die is bonded to the first memory die, creating a compact vertical hierarchy. This nesting approach minimizes the overall device volume while maintaining ease of manufacture through standardized bonding processes.
3Productivity
If memory dies are stacked to increase bandwidth, then performance improves, but the complexity of ensuring proper alignment and bonding increases
Solution Approach 1:
The patent introduces an intermediary base semiconductor die that serves as the foundation for stacking memory dies. This base die provides a stable platform with predefined bonding interfaces and alignment features. The first memory die is bonded to the base die, and the second memory die is bonded to the first memory die, with each interface designed with alignment tolerances that accommodate manufacturing variations. This intermediary structure simplifies the alignment process compared to direct die-to-die bonding, enabling high-precision stacking while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-performance HBM devices with enhanced reliability and reduced joint failure, addressing the need for miniaturization and increased bandwidth in semiconductor technology.
Implementation Method 1
using a gap filling material to pre-bond the dies
Implementation Method 2
The conductive terminals of the first memory die are bonded to the conductive terminals of the semiconductor wafer, and the conductive terminals of the second memory die are bonded to the conductive terminals of the first memory die
Data Source
AI summary
A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.