HBM Redistribution Layer Package Without Silicon Interposer
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Solution Overview
Problem
The manufacturing cost of semiconductor systems is increased due to the use of expensive silicon interposers in conventional high bandwidth memory (HBM) devices with uBumps.
Innovation Solution
A semiconductor package design that includes a plurality of first semiconductor chips stacked vertically, a second semiconductor chip with larger dimensions, a redistribution layer, and connection bumps of varying sizes to reduce system manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon interposers are used in conventional HBM devices, then connection reliability and signal integrity are improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and removes the silicon interposer from the HBM device structure, eliminating the expensive component while maintaining the essential interconnection function through alternative means (direct chip-to-chip stacking with modified bump structures), thereby reducing manufacturing cost without sacrificing connection reliability
Solution Approach 2:
The patent replaces the expensive silicon interposer with a more economical substrate structure that achieves the same interconnection purpose, using cost-effective materials and simpler manufacturing processes to create a functional equivalent that reduces overall system cost
2Productivity
If uBumps with small size and pitch are used, then bandwidth and performance are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the physical parameters of the connection bumps, transitioning from small-sized uBumps with fine pitch to larger bumps with increased pitch. This parameter change maintains the required bandwidth and performance through alternative architectural arrangements while significantly simplifying manufacturing processes and reducing complexity
3Productivity
If semiconductor chips are stacked vertically to increase capacity, then system performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the vertical stacking into manageable units with standardized interfaces, allowing for modular assembly that reduces the cumulative precision requirements. By dividing the multi-chip stack into sections with intermediate connection structures, the overall stacking precision demand is broken down into smaller, more achievable tolerance ranges
Solution Approach 2:
The patent introduces intermediary connection structures and alignment features between stacked chips that act as mediators to compensate for dimensional variations and misalignments. These intermediary elements provide tolerance absorption and self-alignment mechanisms that reduce the stringency of manufacturing precision requirements while enabling successful vertical stacking
Data Source
AI summary
A semiconductor package includes a plurality of first semiconductor chips sequentially stacked in a vertical direction, and connected to each other via a plurality of first through electrodes, each of the plurality of first semiconductor chips having a first width in a horizontal direction, a second semiconductor chip under the plurality of first semiconductor chips, and connected to the plurality of first semiconductor chips via a plurality of second through electrodes, the second semiconductor chip having a second width in the horizontal direction, the second width being greater than the first width, a redistribution layer under the second semiconductor chip, the redistribution layer having a third width in the horizontal direction, the third width being substantially equal to the second width, and a plurality of first connection bumps between the second semiconductor chip and the redistribution layer.