HBM PoP DRAM Pillar-Brick Interconnects for Tight Pitch and Heat Flow
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Solution Overview
Problem
The integration of high-bandwidth memory (HBM) package-on-package (PoP) systems in mobile/edge devices is restricted by reduced form factor dimensions and thermal limitations, which limit the scaling of conductive pillar pitch due to aspect ratio restrictions, hindering effective vertical connections and thermal conduction.
Innovation Solution
A system-in-package (SIP) design utilizing semiconductor pillar bricks with through silicon vias (TSVs) as vertical bridges between logic and memory packages, enabling tighter pitch connections and improved thermal conduction through a high-bandwidth memory (HBM) package-on-package (PoP) integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional conductive pillars are used for vertical connections, then package-to-package connections are established, but the pitch scaling is restricted due to aspect ratio limitations
Solution Approach 1:
The conductive connection path is segmented into multiple sections: conductive pillars within the first package substrate, intermediary conductive structures in the molding compound, and conductive pillars in the second package substrate. This segmentation allows each section to be optimized independently, enabling tighter overall pitch scaling without being constrained by the aspect ratio of a single continuous pillar.
Solution Approach 2:
The molding compound serves as an intermediary medium containing conductive structures that bridge the gap between the conductive pillars of the first package substrate and the conductive pillars of the second package substrate. This intermediary approach allows for pitch reduction by distributing the connection path across multiple components rather than relying on a single high aspect-ratio pillar.
2Productivity
If HBM PoP integration is implemented in mobile devices, then high-bandwidth memory performance is achieved, but thermal limitations are exceeded
Solution Approach 1:
The molding compound acts as a thermal intermediary between the logic die and memory dies, providing a thermally conductive path that dissipates heat generated by high-bandwidth memory operations. This allows the system to maintain high memory bandwidth performance while managing thermal constraints through the thermal management properties of the molding compound.
3Ease of operation
If thicker die is placed at the bottom of PoP, then logic functionality is provided, but conductive pillar pitch scaling is restricted
Solution Approach 1:
The connection architecture is segmented so that the thicker bottom die can accommodate standard conductive pillars, while the pitch reduction is achieved through the intermediary conductive structures in the molding compound and the conductive pillars in the top package substrate. This allows the bottom die thickness to be optimized for logic functionality without directly constraining the final pitch scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SIP design allows for tighter pitch vertical connections and enhanced thermal conduction, overcoming thermal limitations and facilitating high-bandwidth memory integration in mobile/edge devices.
Implementation Method 1
enhanced thermal conduction
Data Source
AI summary
A system-in-package (SIP) is described. The SIP includes a first package substrate supporting a logic die. The SIP also includes a second package substrate supporting a stack of memory dies. The SIP further includes semiconductor pillar bricks coupled between the first package substrate and the second package substrate.