HBM Memory Stack Power Distribution for Uniform Die Communication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the number of stacked layers in High Bandwidth Memory (HBM) increases, communication delays between memory dies and the logical die become uneven, affecting operation speed, and the power supply method impacts semiconductor performance.
Innovation Solution
A semiconductor structure with memory dies stacked parallel to the base, featuring power-supply distribution layers and wire bonds connected to lead frames, which standardize power supply paths and reduce communication delays by ensuring uniform communication distances and improving power supply reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are stacked vertically to increase integration density, then memory capacity and bandwidth are improved, but communication delays become uneven and operation speed deteriorates
Solution Approach 1:
The patent transitions from vertical stacking (one dimension) to horizontal/parallel stacking (another dimension) by arranging memory dies in a planar configuration on the base. This dimensional change allows all memory dies to be positioned at approximately the same distance from the logical die, uniformizing communication delays while maintaining high integration density through increased die count in the parallel arrangement.
2Productivity
If more memory dies are stacked to achieve high bandwidth, then memory capacity increases, but power supply reliability deteriorates due to increased complexity
Solution Approach 1:
The patent divides the power supply system into separate independent power supply paths for each memory die, with each path connecting directly to the base. This segmentation allows each memory die to have its own dedicated power supply route, reducing the impact of power distribution issues on other dies and improving overall power supply reliability in high-density configurations.
Solution Approach 2:
The patent introduces a base as an intermediary platform that provides centralized power ports and power supply paths. This intermediary base structure manages power distribution to multiple memory dies systematically, ensuring stable and reliable power supply while enabling high bandwidth operations through improved power management.
3Device complexity
If memory dies are arranged in traditional vertical stacking, then integration is improved, but communication distance uniformity deteriorates
Solution Approach 1:
The patent employs parallel/planar arrangement of memory dies on the base instead of vertical stacking, changing the spatial dimension from three-dimensional vertical to two-dimensional horizontal. This allows all memory dies to maintain uniform communication distance with the logical die, achieving both high integration and precise communication distance uniformity.
Data Source
AI summary
Provided are a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a base having power ports, a memory module located on the base and including a plurality of memory dies stacked along a first direction, in which each of the memory dies has power-supply signal wires, at least one of the memory dies has a power-supply distribution layer, the power-supply signal wires are electrically connected with the power-supply distribution layer, the power-supply distribution layer includes a first distribution layer and a second distribution layer connected with each other, a plane of the first distribution layer is perpendicular to an upper surface of the base, the second distribution layer is located on a surface of the memory die away from the base; wire bonds connected with the second distribution layer; at least one lead frame connected with the wire bonds and the power ports.