High Bandwidth Memory Processing Element Controllers

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Solution Overview

Problem

Current high bandwidth memory systems rely on external control units for processing operations, limiting their ability to perform simultaneous processing operations internally and potentially slowing down data processing and increasing power consumption.

Innovation Solution

A high bandwidth memory system with a buffer die and multiple memory dies, each containing first and second processing element bank groups, where processing element controllers perform independent processing operations on data using global input/output lines and a data bus, allowing for simultaneous internal processing without external data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If processing operations are performed externally by control units, then device complexity is reduced, but processing speed decreases and power consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the processing functions with the memory system by integrating processing element controllers directly into the memory dies. This allows processing operations to be performed within the memory system itself rather than externally, thereby improving processing speed while managing complexity through functional integration.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory system performs processing operations on its own stored data through integrated processing element controllers, enabling self-service processing without requiring external control units for each operation. This reduces the need for external processing infrastructure and improves overall system efficiency.

Inventive Principle:
Principle #25Self-service

2Productivity

If multiple processing operations are performed simultaneously internally, then productivity increases, but device complexity increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidmemory system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory system is segmented into multiple independent processing element controllers, each capable of performing processing operations independently on different data sets. This segmentation enables simultaneous processing operations across multiple controllers, increasing productivity while managing complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each processing element controller is designed to perform multiple types of processing operations on data stored in the memory system. This multi-functionality allows a single controller to handle various processing tasks, increasing productivity without proportionally increasing the number of components and overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If data is processed externally, then manufacturing precision requirements are reduced, but power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidintegration precision
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

By merging processing functions with memory storage in the same integrated package, the patent eliminates the need for external data transmission and processing. This reduces power consumption significantly while the manufacturing precision challenges are addressed through standard integrated circuit fabrication processes designed for such multi-functional integration.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11355181B2High bandwidth memory and system having the same
Publication Date: 2022.06.07 SAMSUNG ELECTRONICS CO LTD
  • US11355181B2 patent drawing
  • US11355181B2 patent drawing
  • US11355181B2 patent drawing

AI summary

A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.