HBM RAS Cache Architecture for Memory Error Correction
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Solution Overview
Problem
High-bandwidth memory (HBM) systems face challenges in efficiently managing memory errors, particularly in maintaining memory reliability, accessibility, and serviceability (RAS) due to the high number of connections and the resulting increased cost and reduced memory capacity.
Innovation Solution
The implementation of a RAS cache architecture within the HBM system, which includes a spare memory and an address table to map error-prone memory addresses to spare storage, allowing for seamless data access and error correction without reducing memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error handling methods (blacklisting) are used in HBM systems, then memory reliability is improved, but memory capacity is reduced
Solution Approach 1:
The memory system is segmented into regular memory cells and a separate spare memory region. The spare memory is further divided into spare rows and spare columns, creating a modular error correction structure that preserves most of the regular memory capacity while providing targeted error handling capabilities.
Solution Approach 2:
An address translation mechanism acts as an intermediary between the logical address space and physical memory locations. When an error is detected in a regular memory cell, the address translation system redirects accesses to the corresponding location in the spare memory, preventing capacity loss while maintaining reliability.
2Speed
If more connections are made in HBM memory bus to increase bandwidth, then data transfer speed is improved, but cost increases
Solution Approach 1:
The memory architecture transitions from a two-dimensional planar layout to a three-dimensional stacked configuration. Multiple memory dies are stacked vertically and interconnected through through-silicon vias (TSVs), enabling high bandwidth without proportionally increasing the number of external connections required.
Solution Approach 2:
Multiple memory dies are merged into a single stacked memory unit with a shared control interface. The memory controller on one die manages all dies in the stack, reducing the total number of controllers needed and simplifying the external connection architecture while maintaining high internal bandwidth.
Data Source
AI summary
According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.