HBM Signal Delay Architecture for High-Speed Stream Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing technologies face challenges in efficiently delaying high-speed constant bitrate signals without noticeable throughput decrease or interruption, particularly in optical transport networking systems, due to limitations in memory throughput and synchronization requirements.
Innovation Solution
A delay apparatus utilizing a high bandwidth memory (HBM) with demultiplexing and multiplexing operations via multiple channels to temporarily store and retrieve data units, ensuring seamless data stream synchronization across multiple transmission lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is temporarily stored in memory to delay high-speed signals, then synchronization is achieved, but memory throughput limitations cause noticeable decrease in throughput
Solution Approach 1:
The incoming data stream is divided into multiple parallel channels through demultiplexing. Each channel processes data independently through the HBM, allowing concurrent access to multiple memory banks. This segmentation enables the system to achieve the required delay for synchronization while maintaining high throughput by utilizing the parallel architecture of the HBM memory system.
Solution Approach 2:
The patent transitions from a single-channel sequential memory access architecture to a multi-channel parallel architecture. By adding the dimension of parallelism through multiple memory channels and banks, the system simultaneously achieves both synchronization (through proper timing control) and high throughput (through concurrent data transfers).
2Quantity of substance
If conventional memory is used for delaying high-speed signals, then data storage is achieved, but interruption occurs between read and write requests
Solution Approach 1:
The system performs preliminary demultiplexing of the incoming data stream into multiple channels before writing to memory. This preliminary action organizes data into parallel streams that can be independently managed, ensuring that write operations on one channel do not block read operations on other channels, thus maintaining continuous data flow without interruptions.
Solution Approach 2:
The multi-channel architecture enables continuous data processing by allowing overlapping read and write operations across different channels. While one channel is being written to, another channel can be read from simultaneously, ensuring that the useful action of data transmission continues without interruption or idle time.
3Loss of time
If high-speed constant bitrate signals are delayed using traditional methods, then temporal data storage is achieved, but noticeable decrease of throughput occurs
Solution Approach 1:
The data stream is segmented into multiple parallel channels, each handling a portion of the total data rate. This segmentation allows the system to implement delay across multiple channels simultaneously, achieving the required temporal storage while maintaining the overall throughput by distributing the data rate across parallel paths rather than bottlenecking through a single memory interface.
Solution Approach 2:
The patent changes the operational parameters of the memory system by utilizing HBM's high bandwidth capabilities and multi-channel architecture. By adjusting the data distribution across multiple channels and utilizing the memory's high throughput parameters, the system achieves the necessary delay time without sacrificing the high-speed data rate of the original signal.
Data Source
Figure 1~3
Figure 4
Figure 5
AI summary
The invention provides an improved apparatus and method for delaying high-speed constant bitrate signals in a programmable manner. For this purpose, a signal is demultiplexed into individual data units, and the data units are temporarily stored in a high bandwidth memory by writing and reading via multi-channel first data transfer. In this way, the temporary storage of data can be achieved without noticeable decrease of memory throughput and without interruption between writing and reading requests.