HBM Chip Stack Packaging With Staged Bonding and Warpage Control
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Solution Overview
Problem
The bonding state between memory chips in high bandwidth memory (HBM) packages needs enhancement to improve performance.
Innovation Solution
A semiconductor package design with multiple stacked semiconductor chip structures and a molding member, utilizing adhesion layers and conductive connection members to enhance electrical connections and prevent warpage, including a TCB and mass reflow process for bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory chips are stacked vertically to increase bandwidth, then the bandwidth and storage capacity are improved, but the bonding state between chips deteriorates and warpage increases
Solution Approach 1:
The patent divides the bonding process into two distinct stages: TCB bonding for initial chip attachment and mass reflow bonding for final inter-chip connection. This segmentation allows each bonding stage to be optimized independently, preventing bonding deterioration while maintaining high stacking density for improved bandwidth.
Solution Approach 2:
The patent applies preliminary TCB bonding to attach memory chips to the logic chip before performing the mass reflow process. This preliminary action establishes a stable base structure that prevents warpage and bonding deterioration during the subsequent heating and bonding processes.
2Strength
If adhesion layers are used to bond memory chips, then the bonding strength is improved, but electrical connection quality deteriorates
Solution Approach 1:
The patent introduces a dedicated bonding layer as an intermediary between the adhesion layer and the conductive bumps. This bonding layer specifically facilitates electrical connection between chips while the adhesion layer provides mechanical bonding strength, resolving the contradiction between strong bonding and good electrical connection.
Solution Approach 2:
The patent applies different material properties to different regions: the adhesion layer provides strong mechanical bonding, while the bonding layer provides optimal electrical conductivity. This local differentiation of material quality ensures both strong bonding strength and high-quality electrical connections simultaneously.
3Productivity
If chip area is reduced to fit more chips in vertical stack, then the integration density is improved, but warpage control becomes difficult
Solution Approach 1:
The patent controls warpage by precisely managing process parameters including heating temperature, cooling rate, and bonding pressure during both TCB and mass reflow processes. These parameter changes allow small chips to be bonded effectively without excessive warpage, maintaining high integration density.
Solution Approach 2:
The patent employs preliminary TCB bonding to create a stable structural foundation before the mass reflow process. This beforehand cushioning prevents warpage from developing during subsequent processing, allowing smaller chips to be stacked densely without compromising structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances electrical characteristics and reduces warpage, leading to improved electrical connections and efficient bonding of semiconductor chips.
Implementation Method 1
a first adhesion layer between the first and second semiconductor chips and bonding the first and second semiconductor chips to each other
Implementation Method 2
a first conductive connection member between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips to each other
Implementation Method 3
The molding member may be on the first semiconductor chip, and may cover sidewalls of the first adhesion layer, the second semiconductor chip, and the second and third semiconductor chip stack structures
Data Source
AI summary
A semiconductor package includes first, second and third semiconductor chip stack structures and a molding member. The first semiconductor chip stack structure includes first and second semiconductor chips having first and second planar areas and a first adhesion layer therebetween. The second semiconductor chip stack structure is on and bonded with the first semiconductor chip stack structure, and includes third and fourth semiconductor chips having a third planar area and the second planar area and a second adhesion layer therebetween. The third semiconductor chip stack structure is on the second semiconductor chip stack structure, and includes fifth and sixth semiconductor chips having the third planar area and the second planar area, and a third adhesion layer therebetween. The molding member is on the first semiconductor chip, and covers sidewalls of the first adhesion layer, the second semiconductor chip, and the second and third semiconductor chip stack structures.