HBM Stack Access Control via Bypass Circuit and SGID
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Solution Overview
Problem
Conventional 3D memory devices, such as High Bandwidth Memory (HBM), face challenges in optimizing data access speed, power consumption, and chip size reduction due to complex interconnects and signal management across stacked dies.
Innovation Solution
The implementation of a bypass circuit within the HBM stack that includes a command circuit, a stack identifier (SID) circuit, and a match circuit to manage command signals and data strobe signals across different stack groups, allowing for independent operation and efficient data transmission through through-silicon vias (TSVs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional HBM stack architecture is used with multiple core dies and TSV interconnects, then bandwidth and chip size reduction are improved, but signal management complexity and power consumption increase
Solution Approach 1:
The HBM stack is divided into multiple independent stack groups (e.g., stack group 0 and stack group 1), each with its own command circuit and data strobe signal. This segmentation allows parallel operation of multiple stacks, increasing bandwidth while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent introduces stack group identification (SGID) to add a new dimension of organization beyond individual stack identification. This hierarchical addressing scheme (SGID + SID) enables management of multiple stacks in a structured way, improving signal management efficiency as systems scale to more stacks.
2Speed
If multiple data strobe signals are used for independent stack operation, then data access speed is improved, but power consumption increases
Solution Approach 1:
Data strobe signals are activated periodically and selectively based on which stack group is being accessed. The command circuit generates data strobe signals only for the active stack group, allowing parallel data access when needed while reducing power consumption during idle periods or when accessing only one stack group.
3Device complexity
If conventional command routing is used without bypass circuit, then device complexity is reduced, but data access speed decreases
Solution Approach 1:
A bypass circuit is introduced as an intermediary component that receives commands from the interface die and rapidly routes them to the appropriate stack group based on SGID. This bypass circuit provides a direct, high-speed command path that avoids conventional routing delays, improving data access speed while adding minimal complexity.
4Speed
If precise control over data strobe signals is implemented, then data access speed is improved, but device complexity increases
Solution Approach 1:
The command circuit is designed with multi-functionality to handle both stack group identification (SGID) and individual stack identification (SID). This universal command circuit can generate appropriate data strobe signals for any stack group, reducing the need for separate control logic for each stack and managing complexity through consolidated design.
Data Source
AI summary
An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.