HBM Memory Stack Layout for Uniform Delay and Stable Power
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Solution Overview
Problem
The performance of high bandwidth memory (HBM) semiconductor structures is hindered by unequal communication distances and power supply instability as the number of stacked layers increases, leading to delayed communication and reduced operating speed.
Innovation Solution
The memory chips are stacked parallel to the substrate, with power supply wiring layers leading out signal lines and solder bumps connecting to a lead frame, ensuring equal communication distances and stable wired power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked vertically (perpendicular to substrate), then integration density is improved, but communication distance becomes unequal and communication delay increases
Solution Approach 1:
The patent transitions from vertical stacking (perpendicular to substrate) to parallel stacking (parallel to substrate), changing the dimensional orientation of chip arrangement. This dimensional change allows all chips to maintain equal distance from the substrate, ensuring uniform communication delay while achieving high integration density through increased stacking layers.
2Device complexity
If wireless power supply is used in stacked memory chips, then device complexity is reduced, but power supply stability and reliability deteriorate
Solution Approach 1:
The patent extracts the power supply signal lines from the internal wiring of each chip and leads them outward through dedicated power supply wiring layers. This extraction allows for separate, controlled power supply paths that can be individually optimized and stabilized, improving reliability while maintaining manageable complexity through systematic organization.
Solution Approach 2:
The patent introduces power supply wiring layers as intermediary structures between the substrate and the memory chips. These wiring layers serve as dedicated conduits for power supply signals, providing stable and reliable power distribution while isolating the power supply paths from other signal lines, thereby reducing interference and improving overall system reliability.
3Quantity of substance
If number of stacked layers is increased, then memory capacity is improved, but structural strength and connection reliability deteriorate
Solution Approach 1:
By arranging chips in parallel layers rather than vertical stacking, the patent distributes structural stress across a larger area parallel to the substrate. This dimensional arrangement reduces the mechanical load on individual connection points while maintaining high memory capacity through increased layer count.
Solution Approach 2:
The patent incorporates solder bumps and lead frames in advance during the manufacturing process, creating robust mechanical and electrical connections before the stacking assembly is completed. This preliminary establishment of strong connection structures ensures that even as the number of layers increases, the overall structural integrity and connection reliability are maintained.
Data Source
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AI summary
Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure and a fabricating method of a semiconductor structure. The semiconductor structure includes: a substrate having a power supply port; a memory module positioned on an upper surface of the substrate, where the memory module includes memory chips stacked in a first direction, the first direction is parallel to the upper surface of the substrate, each of the memory chips has a power supply signal line, at least one of the memory chips has a power supply wiring layer, the power supply signal line is electrically connected to the power supply wiring layer, the power supply wiring layer is positioned in the memory module, an end surface of the power supply wiring layer far away from the substrate is exposed by the memory module, and a solder bump is further provided on the end surface; and a lead frame electrically connected to the solder bump and the power supply port. The embodiments of the present application can at least improve the performance of the semiconductor structure.