HBM Stack Packaging With Mixed Bonding for Low-Height Interconnects
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Solution Overview
Problem
Current multi-layer stacked memory packaging technologies face limitations in increasing storage capacity and data throughput speed due to the constraints of spacing and height in the micro-bump structure, leading to reliability issues and limited room for improvement.
Innovation Solution
A packaging method and structure that uses mixed-bonding between memory chips, forming memory micro-modules with conductive vias and bumps, and a plastic encapsulation layer to stack and connect the chips, reducing the bonding height and increasing the number of chip layers while minimizing yield loss and production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between bumps is reduced to increase the number of stacked layers, then the storage capacity increases, but the tin will be fully converted into intermetallic compound under thermal load conditions, leading to reliability failure
Solution Approach 1:
The patent changes the material parameter of the bump from traditional copper-tin to copper-nickel-gold composite structure. This parameter change allows the bump to maintain structural integrity at reduced spacings (below 25 μm) by preventing complete tin conversion to intermetallic compounds, thus enabling increased storage capacity while maintaining reliability under thermal load conditions.
Solution Approach 2:
The patent employs a composite material structure for the bump consisting of copper, nickel, and gold layers. This composite structure combines the advantages of each material: copper provides conductivity, nickel provides strength and diffusion barrier, and gold provides corrosion resistance. This composite approach resolves the contradiction by enabling smaller bump spacing without compromising reliability.
2Quantity of substance
If the number of stacked layers is increased to increase storage capacity, then the storage capacity increases, but the bonding height limitation restricts further improvement
Solution Approach 1:
The patent changes the bonding interface material composition to copper-nickel-gold, which enables thinner and more reliable bonding interfaces. This parameter change reduces the effective bonding height requirement, allowing more chip layers to be stacked within the same vertical space, thus increasing storage capacity while overcoming the bonding height limitation.
3Productivity
If the bump spacing is reduced to increase pin density, then the data throughput speed increases, but the deformability of tin causes short circuit between bumps
Solution Approach 1:
The patent replaces the single-phase copper-tin bump with a multi-layer copper-nickel-gold composite structure. The nickel and gold layers provide structural rigidity and prevent excessive deformation during reflow, eliminating the short circuit problem that occurs with traditional tin-based bumps when spacing is reduced for higher pin density and data throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased storage capacity and data throughput speed by reducing the bonding height, increasing the number of chip layers, and improving production efficiency while minimizing yield loss and production costs.
Implementation Method 1
the multi-layer chips of the multi-layer stacked memory are stacked by a thermal compression bond (TCB) process. Through rapid heating, a bump is connected to a pad on the back of the chip
Implementation Method 2
In the case of using the copper-tin bump, due to the deformability of tin during reflow
Data Source
AI summary
A packaging method and a packaging structure of a multi-layer stacked high-bandwidth memory are provided. The packaging method includes respectively providing a substrate and a plurality of memory chips. The packaging method also includes sequentially forming a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface of the memory chip; and forming a plurality of pads on a second surface of the memory chip. In addition, the packaging method includes nesting a second conductive bump and a pad on every adjacent two memory chips through a thermal compression bonding process, to insulate and sequentially stack the plurality of memory chips over the substrate. Further, the method includes performing a reflow soldering process on the plurality of stacked memory chips and the substrate; and forming a plastic encapsulation layer to wrap the plurality of memory chips and the substrate.