High-bandwidth Memory Stacked Package Impedance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microelectronic packages occupy a larger area on circuit panels than the chips themselves, posing challenges for compact arrangements in portable devices and data servers where space and interconnection efficiency are critical.
Innovation Solution
A microelectronic assembly design featuring an address bus with signal conductors passing through multiple connection regions, allowing microelectronic packages to be electrically coupled with consistent electrical characteristics, ensuring balanced load and delay across connections, thereby optimizing space usage and interconnection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional microelectronic packages are used, then electrical connections and terminals are provided, but the package occupies a larger area on the circuit panel than the chip itself
Solution Approach 1:
The patent transitions from a conventional two-dimensional package layout to a three-dimensional stacked architecture. Multiple microelectronic elements are vertically stacked and interconnected through vertical conductors (vias) and horizontal conductors (traces) within the same footprint area, effectively utilizing the vertical dimension to reduce the area occupied on the circuit panel while maintaining or enhancing interconnection capabilities
Solution Approach 2:
The patent implements a nested structure where multiple microelectronic elements are stacked vertically within a single package body. The elements are interconnected through conductors that extend through the package structure, creating a compact nested arrangement that reduces the overall area occupied on the circuit panel compared to conventional side-by-side packaging
2Area of stationary object
If multiple chips are packed into a small space, then space efficiency is improved, but the components forming interconnections should not greatly increase the size of the assembly
Solution Approach 1:
The patent divides the interconnection structure into distinct functional segments: vertical conductors (vias) for inter-element connections, horizontal conductors (traces) for signal routing, and terminal structures for external connections. This segmentation allows each component to be optimized independently while maintaining compact overall dimensions
Solution Approach 2:
The patent utilizes the vertical dimension within the package to route conductors between stacked microelectronic elements, rather than requiring extensive horizontal routing. This vertical routing approach reduces the horizontal footprint of the assembly while accommodating multiple interconnections between chips
3Power
If electrical connections are made between stacked microelectronic elements, then bandwidth capability is enhanced, but controlled impedance loading must be maintained for optimal performance
Solution Approach 1:
The patent implements different conductor configurations and materials in different regions of the package to maintain controlled impedance. The trace geometry, width, and spacing are locally optimized based on the specific signal routing requirements and impedance constraints of each connection region
Solution Approach 2:
The patent adjusts physical parameters of the conductors (trace width, spacing, thickness, material composition) to control and maintain characteristic impedance values. These parameter changes are made in response to the specific electrical requirements of different signal paths and loading conditions within the stacked package
Data Source
AI summary
A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.