HBM Write Strobe Phase Control for High-Speed Low-Power Memory

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Solution Overview

Problem

High-speed data transmission in memory devices leads to increased power consumption due to the use of high-frequency data strobe signals.

Innovation Solution

A memory device design with a buffer die and core dies stacked through silicon through electrodes, utilizing a write data strobe signal divider to generate internal strobe signals with different phases, reducing the need for separate synchronization and minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a high-frequency data strobe signal is used for high-speed data transmission, then data transmission speed is improved, but power consumption increases

Engineering Contradiction:

Improvedata transmission speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides the data transmission interface into multiple independent channels, each with its own data strobe signal. This segmentation allows selective activation of channels based on data transmission needs, reducing overall power consumption while maintaining high-speed transmission capability on active channels.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The data strobe signal is designed to toggle periodically between high and low levels, enabling high-speed data transmission only during active periods. This periodic action allows the system to achieve high data rates when needed while potentially entering lower-power states during idle periods, resolving the contradiction between speed and power consumption.

Inventive Principle:

Principle #19Periodic action

2Productivity

If multiple independent channels are implemented for high bandwidth, then data transmission capacity is improved, but device complexity increases

Engineering Contradiction:

Improvedata transmission capacityVSAvoidinterface complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent combines multiple independent channel interfaces into a unified memory device architecture with shared control logic and stacked core dies. This merging approach enables high data transmission capacity across multiple channels while reducing overall device complexity through resource sharing and integrated design.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements multiple channels in a stacked three-dimensional architecture rather than spreading them out in two dimensions. This dimensional change allows high bandwidth across multiple channels while compacting the device structure, effectively managing complexity through vertical integration.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260080934A1Memory device transmitting and receiving data at high speed and low power

Publication Date: 2026.03.19 SAMSUNG ELECTRONICS CO LTD

AI summary

A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.