HBM Switch Chiplet for Semiconductor Package Signal Integrity
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Solution Overview
Problem
Conventional AI semiconductors face challenges in efficiently connecting High Bandwidth Memory (HBM) to Central Processing Units (CPU) or Neural Processing Units (NPU) due to long signal lines with high resistance, limiting data transmission speed and increasing chip size.
Innovation Solution
A semiconductor device with an interposer and HBM switch chiplet that includes perpendicular and shielded connection wires, reducing wire length and resistance to enhance data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the NPU and HBM are connected through a conventional interposer with long signal lines, then the connection is established, but the resistance of the signal line increases and data transmission speed decreases
Solution Approach 1:
The patent transitions from a conventional planar interposer architecture to a three-dimensional stacked architecture. The HBM switch chiplet is positioned vertically beneath the interposer, and signal lines are routed through the interposer thickness rather than across its surface. This dimensional change reduces signal line length from millimeters to tens of micrometers, directly resolving the contradiction between connection establishment and signal line length.
2Productivity
If multiple signal bumps are used for Wide IO configuration, then data bandwidth is improved, but the size of the NPU chiplet increases substantially
Solution Approach 1:
The patent extracts the switching function from the NPU chiplet and relocates it to a separate HBM switch chiplet. By taking out the switch component, the NPU chiplet no longer needs to accommodate thousands of signal bumps for Wide IO configuration. Instead, fewer bumps connect the NPU to the switch chiplet, which then handles the high-bandwidth connections to HBM, thus resolving the contradiction between data bandwidth and chiplet area.
3Reliability
If the signal line length is reduced to improve data transmission speed, then resistance decreases, but the complexity of the interposer structure increases
Solution Approach 1:
The patent introduces an HBM switch chiplet as an intermediary component between the NPU and HBM. This mediator enables short signal lines to achieve high-speed transmission while the interposer's internal wiring handles the routing complexity. The switch chiplet absorbs the structural complexity burden, allowing the signal transmission path to remain simple and short, thus resolving the contradiction between signal transmission reliability and interposer structure complexity.
Data Source
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AI summary
A semiconductor device according to an embodiment of the present disclosure may include an interposer, a High Bandwidth Memory (HBM) module and a semiconductor module disposed to be spaced apart from each other on the top of the interposer, and an HBM switch chiplet disposed under the interposer and configured to electrically connect the HBM module and the semiconductor module.