HBM Test Circuit Bypassing Small Terminals
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Solution Overview
Problem
The existing operation tests for High Bandwidth Memory (HBM) devices are challenging due to the small size of external terminals on the interface chip, making it difficult to perform tests in the same operating environments as normal operation, and there is a need to identify defect locations accurately.
Innovation Solution
A semiconductor device configuration that includes a package substrate, interposer, host controller, and HBM with a direct access terminal allowing direct connection to a bump electrode, enabling the reproduction of normal operating conditions for testing the interface chip and memory core chips independently, using a BIST circuit to generate test signals and decode commands, and bypass/write circuits for accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If external terminals are used for testing, then operation tests can be performed on stacked memory core chips, but the terminals are too small for easy probing and testing is difficult
Solution Approach 1:
The patent introduces a direct access terminal as an intermediary testing interface that connects to larger external terminals on the package substrate. This mediator allows test signals to be transmitted to the interface chip without requiring direct probing of the small external terminals, thus resolving the contradiction between terminal size and ease of probing.
2Reliability
If memory core chips are operated without input/output circuit operation, then testing can be performed independently, but noise from memory core chips is absent creating different test environments from normal operation
Solution Approach 1:
The patent employs dynamic control of circuit operation states through the BIST circuit, which can selectively activate or deactivate the input/output circuit during testing. This dynamic switching capability allows the system to operate in different modes (with or without I/O circuit) depending on the specific test requirements, enabling accurate reproduction of normal operating environments when needed while maintaining testing flexibility.
Solution Approach 2:
The BIST circuit incorporates feedback mechanisms to monitor and control the operation state of the interface chip and memory core chips. This feedback system ensures that the appropriate circuits are activated during testing to reproduce normal operating conditions, including the presence of noise from both the input/output circuit and memory core chips, thereby improving test environment accuracy.
3Reliability
If input/output circuit is operated without memory core chips, then independent testing is possible, but no noise occurs from memory core chips creating different test environments
Solution Approach 1:
The system dynamically adjusts which circuits are operational during testing through BIST control. When defect identification accuracy is prioritized, both the input/output circuit and memory core chips are activated to reproduce normal operating noise environments. When testing flexibility is needed, the system can selectively deactivate specific circuits. This dynamic adaptability resolves the contradiction between reliability and versatility.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.