HBM Wafer Stacking With Control Die Defect Bypass
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently integrating high bandwidth memory (HBM) structures with high density and reliability, particularly in three-dimensional (3D) memory devices, which often require costly die-to-die bonding and result in reduced production yield and increased fabrication costs.
Innovation Solution
The integration of semiconductor devices is achieved through wafer-to-wafer bonding techniques, where wafers are stacked and coupled by contact structures, allowing for monolithic semiconductor structures and the inclusion of a control die to detect and disable defective components, thereby improving reliability and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die-to-die bonding is used to integrate HBM structures, then high density and bandwidth are achieved, but fabrication cost increases and production yield decreases
Solution Approach 1:
The patent segments the HBM integration process into wafer-level bonding stages rather than individual die bonding. Multiple memory dies remain attached to their respective wafers during stacking, and wafer-level bonding is performed to integrate the stacked structures. This segmentation approach maintains high density benefits while enabling more efficient manufacturing with better yield and lower cost.
Solution Approach 2:
The patent transitions from two-dimensional die-to-die bonding to three-dimensional wafer-level stacking. By utilizing the vertical dimension for wafer stacking and implementing bonding at the wafer level rather than individual die level, the process achieves high density while improving manufacturing efficiency, production yield, and reducing fabrication costs.
2Ease of manufacture
If wafer-to-wafer bonding is used for integration, then production yield and ease of manufacture improve, but defective regions cannot be bypassed
Solution Approach 1:
The patent implements preliminary testing and mapping of defective regions at the die level before wafer stacking. Control dies are used to identify and map defective areas in advance. This preliminary action enables the system to later bypass defective regions through adaptive routing and reconfiguration, combining the manufacturing efficiency of wafer-level bonding with the flexibility to manage defects.
Solution Approach 2:
The patent incorporates control dies that provide feedback information about the operational status of memory structures. This feedback mechanism enables real-time detection of defective regions and allows the system to adaptively reroute signals and bypass failures, maintaining high production yield while preserving defect management capability through closed-loop control.
3Power
If high density stacking is implemented, then bandwidth increases, but device complexity increases
Solution Approach 1:
The patent employs control dies that perform multiple functions: testing memory structures, mapping defective regions, managing signal routing, and coordinating data transfer between stacked wafers. This multi-functionality reduces the need for separate dedicated components, thereby managing device complexity while maintaining high bandwidth through dense stacking.
Solution Approach 2:
The patent introduces control dies as intermediary components between the stacked memory wafers and external systems. These control dies simplify the overall system complexity by centralizing control functions, managing the complexity of high-density interconnections, and providing a unified interface for data access while enabling high bandwidth operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration and reliability of HBM devices by enabling large-scale integration with reduced costs, improved production yield, and the ability to bypass defective regions, thus maintaining device functionality.
Implementation Method 1
The bonding layer includes conductive bonding contacts and a dielectric material. The bonding layer is bonded to the wafer
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for managing a high bandwidth memory (HBM). An example semiconductor device includes a control die and wafers stacked together along a first direction. Each of the wafers includes a semiconductor substrate extending along a second direction perpendicular to the first direction and semiconductor structures on a side of the semiconductor substrate. The control die is coupled to the semiconductor structures of each of the wafers by contact structures extending through a corresponding semiconductor substrate of at least one of the wafers along the first direction.