HBM Die Stack Wireless Layout for Inter-Die Delay Reduction
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Solution Overview
Problem
As the number of layers in High Bandwidth Memory (HBM) stacks increases, communication delays between upper and lower die stack structures and the first semiconductor die become significant due to varying distances, leading to technical difficulties in data transmission and integration.
Innovation Solution
The semiconductor package structure incorporates wireless communication portions in both the first semiconductor die and the second semiconductor die stack structure, allowing for wireless communication between the dies to mitigate delays caused by distance differences, with specific communication portions aligned to facilitate efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of die stack layers is increased to improve integration level and bandwidth, then computing capability and bandwidth are improved, but communication delays between upper and lower die stack structures increase due to varying distances
Solution Approach 1:
The patent introduces wireless communication portions that extend communication paths in horizontal directions (second direction perpendicular to stacking direction) alongside vertical communication paths. This multi-dimensional communication approach allows data to travel through alternative paths, reducing the impact of vertical distance variations and communication delays in stacked die structures.
Solution Approach 2:
The wireless communication portions act as intermediary communication channels between different die stack structures. Instead of relying solely on direct vertical communication paths through TSVs, the patent introduces wireless communication as an intermediary mechanism that can bridge communication gaps and reduce delays by providing alternative transmission routes.
2Adaptability or versatility
If more die stack layers are integrated to solve I/O bottleneck, then integration level is improved, but technical difficulties increase due to varying communication distances and delays
Solution Approach 1:
The patent segments the communication system into multiple independent communication paths: wired vertical communication through TSVs and wireless communication portions. This segmentation allows each communication channel to be optimized independently and provides flexibility in managing complex multi-layer die structures by dividing the communication task across different pathways.
Solution Approach 2:
By adding wireless communication portions that operate in directions perpendicular to the stacking direction, the patent creates additional communication dimensions. This multi-dimensional approach simplifies the management of complex inter-die communications by providing alternative routing options that bypass the limitations of purely vertical communication paths.
Data Source
AI summary
A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a first semiconductor die and a second semiconductor die stack structure. A first wireless communication portion is formed in the first semiconductor die. The second semiconductor die stack structure includes a first die stack structure and a second die stack structure. A second wireless communication portion and a third wireless communication portion are respectively formed in two sides, along a second direction, of the first die stack structure. A fourth wireless communication portion is formed in one side, opposite to the first die stack structure, of the second die stack structure. The first direction is a direction parallel to a plane of the first semiconductor die, and the second direction is a direction perpendicular to the plane of the first semiconductor die.