HBT Base Dual-Input Layout for Lower Resistance at High Frequency

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Solution Overview

Problem

The base resistance in heterojunction bipolar transistors (HBTs) affects the maximum operating frequency and device performance, requiring a reduction to achieve higher efficiency, output power, and linearity.

Innovation Solution

A double signal input configuration is introduced at the base terminal, where a new signal input is added to the existing signal input, reducing the base resistance through specific via hole arrangements and conductive layer connections, allowing signal transmission across both sides of the base layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the base resistance is reduced through conventional single signal input configuration, then the maximum operating frequency and device performance are improved, but the stability factor for maximum stable gain and maximum available gain cannot be prolonged towards higher frequencies

Engineering Contradiction:
Improvestability factorVSAvoidmaximum operating frequency
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The base terminal is segmented into two separate signal input paths: a first signal input connected to the base layer through a first via hole, and a second signal input connected through a second via hole. This segmentation allows independent optimization of each input path, enabling the stability factor to be prolonged towards higher frequencies while maintaining low base resistance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional single-dimensional signal input to a two-dimensional dual signal input configuration. The first and second via holes are positioned at different locations (first edge and second edge of the base layer), creating spatial diversity that reduces the effective base resistance and extends the stability factor into higher frequency ranges.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a double signal input configuration is introduced with via holes at both edges of the base layer, then the base resistance is reduced and stability factor is prolonged, but the device structure and fabrication process become more complex

Engineering Contradiction:
Improvebase resistanceVSAvoidvia hole arrangement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dual via hole structure serves multiple functions simultaneously: it reduces base resistance by providing parallel current paths, prolongs the stability factor towards higher frequencies through extended signal paths, and maintains compatibility with standard HBT fabrication processes. The first and second via holes can be integrated into existing dielectric layers without requiring entirely new process steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If via holes are positioned at the edges of the base layer for dual signal input, then the base resistance is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvebase resistanceVSAvoidvia hole positioning
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The via holes are positioned at the first edge and second edge of the base layer, which are predetermined locations that can be defined during the initial design and fabrication planning stages. This preliminary positioning allows for optimized alignment procedures and reduces the complexity of precise positioning during manufacturing, as the edge locations provide natural reference points for alignment.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11990537B2Heterojunction bipolar transistor and power amplifier
Publication Date: 2024.05.21 WIN SEMICON
  • US11990537B2 patent drawing
  • US11990537B2 patent drawing
  • US11990537B2 patent drawing

AI summary

A heterojunction bipolar transistor includes: a substrate; a base mesa disposed on the substrate, wherein the base mesa includes a collector layer and a base layer disposed on the collector layer, and wherein in a top view, the base layer includes a first edge and a second edge opposite to the first edge; an emitter layer disposed on the base layer; a base electrode disposed on the substrate and connected to the base layer; a dielectric layer disposed on the base electrode, wherein a first via hole is formed in the dielectric layer at the first edge of the base layer, and a second via hole is formed in the dielectric layer at the second edge of the base layer; and a conductive feature disposed on the dielectric layer, wherein the conductive feature is connected to the base electrode through the first via hole and the second via hole.