HBT-Integrated SCR Structure for Low-Capacitance RF ESD Protection

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Solution Overview

Problem

Conventional silicon controlled rectifiers (SCRs) used for electrostatic discharge (ESD) protection in integrated circuits (ICs) suffer from high capacitance loading and poor radiofrequency (RF) performance, which can impact the performance of high-performance analog and RF designs.

Innovation Solution

A heterojunction bipolar transistor (HBT) integrated with a silicon controlled rectifier (SCR) is proposed, where the SCR and HBT share a doped semiconductor material above an underlying semiconductor substrate. This structure includes n-type and p-type regions on either side of a shallow trench isolation region, vertically contacted to SiGe materials of opposite doping types, reducing capacitance and RF degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional SCR is used for ESD protection, then high current handling ability is achieved, but capacitance loading increases and RF performance deteriorates

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidcapacitance loading and RF performance degradation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent combines SCR and HBT into a single integrated structure where the HBT's low-capacitance characteristics compensate for the SCR's high capacitance loading, while maintaining the SCR's ESD protection capability. The shared doped semiconductor material and vertical junction architecture enable both devices to coexist on the same substrate with improved overall RF performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integration uses composite semiconductor structures with different doped regions (n-type and p-type) arranged vertically to create both SCR and HBT functions. The heterojunction bipolar transistor incorporates different semiconductor materials with opposite doping types to achieve low capacitance while the silicon controlled rectifier provides high current handling for ESD protection.

Inventive Principle:
Principle #40Composite materials

2Reliability

If SCR is used to protect antenna ports, then ESD protection is provided, but RF performance is impacted due to capacitance loading

Engineering Contradiction:
Improveantenna port protectionVSAvoidRF performance impact
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent merges SCR and HBT functions in a single integrated device that protects antenna ports while maintaining RF performance. The HBT component provides low capacitance characteristics that reduce RF degradation, while the SCR component maintains ESD protection capability for antenna ports.

Inventive Principle:
Principle #5Merging (Combining)

3Object-affected harmful factors

If HBT is integrated with SCR, then capacitance is reduced and RF performance is improved, but device structure becomes more complex

Engineering Contradiction:
Improvecapacitance and RF degradationVSAvoidintegrated structure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent reduces device complexity by merging SCR and HBT into a single integrated structure that shares common doped semiconductor material and vertical junctions. This unified architecture achieves low capacitance and improved RF performance without requiring separate discrete devices, thereby managing structural complexity efficiently.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The integration of HBT with SCR achieves lower capacitance, reduced RF degradation, fast switching time, and higher current drive due to improved beta of the heterojunction bipolar transistor, effectively addressing the limitations of conventional SCRs.

Implementation Method 1

a heterojunction bipolar transistor integrated with a silicon controlled rectifier which share a doped semiconductor material above an underlying semiconductor substrate, the doped semiconductor material acting as base of the heterojunction bipolar transistor and which is isolated from an underlying well of a same dopant type by an opposite dopant type region in the underlying semiconductor substrate

Methodology Applied
Scientific EffectHeterojunction:

Implementation Method 2

the doped semiconductor material acting as base of the heterojunction bipolar transistor and which is isolated from an underlying well of a same dopant type by an opposite dopant type region in the underlying semiconductor substrate

Methodology Applied
Scientific EffectDoping isolation: Dopants

Data Source

PatentUS20250185265A1Silicon controlled rectifier integrated heterojunction bipolar transistor
Publication Date: 2025.06.05 GLOBALFOUNDRIES US INC
  • US20250185265A1 patent drawing
  • US20250185265A1 patent drawing
  • US20250185265A1 patent drawing

AI summary

The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor integrated silicon controlled rectifier and methods of manufacture. The structure includes: a first region having a first dopant type provided in a semiconductor substrate; a second region having a second dopant type provided in the semiconductor substrate; an isolation region between the first region and the second region; a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite from the first dopant type; a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite from the second dopant type; a polysilicon material vertically contacting the first semiconductor layer; and a single crystalline semiconductor material vertically contacting the first semiconductor layer and the second semiconductor layer.