Heterojunction Bipolar Transistor Self-Aligned Epitaxial Base
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Solution Overview
Problem
Existing HBT manufacturing methods face challenges in reducing device size, simplifying the manufacturing process, and enhancing performance metrics such as maximum oscillation frequency, bandwidth, and minimum noise, particularly due to limitations in collector-base capacitance and total base resistance.
Innovation Solution
The method involves self-aligned epitaxial silicon-germanium formation overlapping with STI structures, allowing for easier manufacturing and improved properties, and is fully compatible with conventional CMOS processing, with the option to include carbon in the silicon-germanium layer to reduce boron-doped base outdiffusion and adjust collector drift region thickness for high-frequency or high-voltage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional HBT manufacturing methods are used, then manufacturing cost is reduced, but device size cannot be further reduced and performance metrics (maximum oscillation frequency, bandwidth) are limited
Solution Approach 1:
The base window is formed to overlap with the STI structures, enabling self-aligned epitaxial silicon-germanium formation. This self-alignment eliminates the need for additional alignment steps and complex patterning processes, allowing device size reduction while maintaining manufacturing simplicity and cost-effectiveness
Solution Approach 2:
The base window is positioned in a overlapping region with STI structures, utilizing the vertical dimension and lateral overlap to achieve self-alignment. This dimensional approach enables precise positioning without additional alignment steps, facilitating smaller device dimensions while maintaining manufacturing ease
2Device complexity
If conventional HBT manufacturing methods are used, then manufacturing simplicity is maintained, but collector-base capacitance and total base resistance limit performance enhancement
Solution Approach 1:
The self-aligned epitaxial growth process automatically positions the silicon-germanium layer relative to the collector drift region through the overlapping base window configuration. This eliminates complex alignment procedures while enabling optimized device geometry that reduces collector-base capacitance and base resistance, thereby improving performance metrics without increasing manufacturing complexity
Solution Approach 2:
The overlapping base window configuration enables precise control of the collector drift region geometry and the epitaxial layer positioning. By adjusting the overlap dimensions and epitaxial growth parameters, the device achieves optimized electrical characteristics including reduced collector-base capacitance and lower base resistance, enhancing performance without complicating the manufacturing process
3Ease of manufacture
If temperature processing is performed for bipolar manufacturing, then bipolar devices are formed, but CMOS parameters are influenced and gate-oxide breakdown risk increases
Solution Approach 1:
The bipolar device structure is formed using the self-aligned epitaxial process before CMOS gates are patterned and before critical CMOS implantations are carried out. This preliminary formation allows subsequent CMOS processing to be performed at lower temperatures that do not affect the already-formed bipolar structure, protecting CMOS parameters and gate-oxide integrity
Solution Approach 2:
The manufacturing process is segmented into distinct stages: first forming the bipolar device structure with self-aligned epitaxial growth, then proceeding with CMOS processing. This segmentation isolates the high-temperature bipolar formation step from subsequent CMOS steps, preventing thermal damage to CMOS components while maintaining ease of bipolar device formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved high-frequency and high-voltage properties, reduced base resistance, and scalability for future CMOS generations, while maintaining compatibility with CMOS performance and reducing the risk of gate-oxide breakdown.
Implementation Method 1
A layer 108 is then grown in the base window using a non-selective epitaxial process that grows epitaxial SiGeC 110 above the collector region
Implementation Method 2
The deposited silicon-germanium may further comprise carbon. This can reduce the outdiffusion from the boron-doped base during subsequent CMOS procesing steps, in particular the temperature processing associated with such CMOS steps
Data Source
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AI summary
A heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures 6 around a buried collector drift region 8 in contact with a buried collector. A gate stack 10 including a gate oxide 12 and a gate 14 is deposited and etched to define a base window 20 over the buried collector drift region 8 and overlapping the STI structures 6. The etching process is continued to selectively etch the buried collector drift region 8between the STI structures 6 to form a base well 22. SiGeC may be selectively deposited to form epitaxial silicon-germanium 26 in the base well in contact with the buried collector drift region 8 and poly silicon-germanium 28 on the side walls of the base well and base window. Spacers 32 are then formed as well as an emitter 34.