HDD SOC with Host Buffering via High-Speed Interface
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Solution Overview
Problem
Current hard disk drive (HDD) systems-on-chip (SOC) architectures require separate designs for desktop and enterprise applications, leading to increased design inventory and die costs due to differences in processors and interfaces, and they often rely on local low-latency RAM for buffering, which is costly and inflexible.
Innovation Solution
A HDD SOC that incorporates a high-speed interface for communication with a host device, allowing the use of volatile memory on the host device for additional buffering, and a bridge chip for interface conversion between SATA and SAS/FC, enabling flexible buffer memory allocation and reducing the need for local memory on the HDD SOC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate HDD SOC designs are used for desktop and enterprise applications, then application-specific performance requirements are met, but design inventory and die costs increase
Solution Approach 1:
The patent implements a universal HDD SOC design that can function in both desktop and enterprise applications through a single device architecture. The controller is designed to support multiple interface types (SATA and SAS/FC) and can dynamically allocate buffer memory between local and host-based storage, allowing the same hardware platform to serve different application requirements without requiring separate designs.
Solution Approach 2:
The patent employs dynamic buffer memory allocation where the controller can adaptively manage memory resources based on operational needs. The buffer memory can be dynamically allocated between local caching and host-based buffering, and the interface type can be dynamically selected between SATA and SAS/FC, enabling the system to optimize performance for different applications in real-time rather than being fixed to a single configuration.
2Productivity
If local low-latency RAM is used for buffering in HDD SOC, then data buffering performance is improved, but cost and flexibility deteriorate
Solution Approach 1:
The patent segments the buffer memory into two distinct parts: local buffer memory integrated with the HDD SOC and host-based buffer memory in the host system. This segmentation allows the local memory to handle time-critical buffering operations requiring low latency, while the host-based memory provides additional flexible capacity. The controller manages both segments independently, allocating data to appropriate buffer locations based on performance requirements and available resources.
Solution Approach 2:
The HDD controller acts as an intermediary between the local buffer memory and host-based buffer memory, managing data transfer and buffer allocation. The controller can selectively store buffer data in either the local memory or transmit it to host memory via high-speed interfaces, mediating between the performance requirements of local access and the flexibility/capacity of host-based storage without requiring a single memory type to satisfy all requirements.
3Adaptability or versatility
If host-based buffering is implemented, then flexibility and inventory costs are reduced, but interface speed and data transfer efficiency must be maintained
Solution Approach 1:
The patent implements multiple interface types (SATA and SAS/FC) with different speed characteristics and protocol parameters. The controller can dynamically select and switch between these interfaces based on the host system's capabilities and the specific operational requirements. By changing interface parameters and selecting appropriate protocols, the system maintains high data transfer speeds while enabling host-based buffering flexibility, as the faster interfaces can compensate for the increased data transfer distance to host memory.
Data Source
AI summary
A circuit for a storage device that communicates with a host device comprises a first high speed interface. A storage controller communicates with the high speed interface. A buffer communicates with the storage controller. The storage device generates storage buffer data during operation. The storage controller is adapted to selectively store the storage buffer data in at least one of the buffer and/or in the host device via the high speed interface. A bridge chip for enterprise applications couples the circuit to an enterprise device.