Focused HDL and FPGA Verification via Stimulus Files
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Solution Overview
Problem
The existing methods for verifying and testing circuit designs using hardware description languages (HDL) and field-programmable gate arrays (FPGA) are time-consuming, as they require lengthy simulations to reproduce and fix errors, leading to inefficient debugging and verification processes.
Innovation Solution
A method and system that generate a stimulus file based on waveform data to reproduce circuit design errors in a shorter duration, allowing for focused simulations that identify and fix issues more quickly, using a processor to configure and perform simulations within an FPGA environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full circuit design simulation is performed to verify functionality and reproduce errors, then verification completeness is improved, but simulation time increases
Solution Approach 1:
The patent segments the circuit design into multiple hierarchical levels (top-level module, sub-modules, individual circuits). The stimulus file enables selective simulation at specific levels rather than requiring complete full-circuit simulation, thus reducing simulation time while maintaining verification effectiveness for targeted error reproduction
Solution Approach 2:
The patent extracts and isolates the specific error condition from the complete circuit design. By using waveform data to identify problematic signal sequences and creating targeted stimulus files that reproduce only the erroneous conditions, the system extracts the essential verification need without requiring simulation of the entire circuit design
2Measurement precision
If detailed waveform data from full simulation is analyzed to reproduce errors, then error reproduction accuracy is improved, but processing time and computational resources increase
Solution Approach 1:
The patent creates a simplified copy of the error-reproducing conditions rather than analyzing complete waveform data. The stimulus file copies only the essential signal sequences and test conditions needed to reproduce the error, eliminating the need to process and store extensive waveform information while maintaining accurate error reproduction
Solution Approach 2:
The patent performs preliminary analysis during the initial simulation to identify error conditions and extract relevant waveform characteristics. This preliminary action captures the essential error information that can then be used to create targeted stimulus files, avoiding the need for repeated detailed waveform analysis
Data Source
AI summary
The disclosure discloses various systems, apparatuses, devices, and methods for verification and testing of hardware description language (HDL) and field-programmable gate array (FPGA) designs. A waveform dump generated in a verification environment or in-FPGA environment can be used to prepare a stimulus file that is configured to reduce the time needed to fix an error/issue found in an HDL/FPGA design. In the verification environment, the stimulus file can reduce the simulation time of an HDL design needed to reproduce the error/issue encountered in a full cycle simulation. Similarly, in the in-FPGA environment, the stimulus file can reduce the simulation time needed to reproduce the error/issue encountered in the FPGA hardware test. In both cases, the techniques for configuring stimulus file can accelerate the process of debugging, testing, and verifying a design using simulation.