HDL Code Generation With AST Waveform Tracing Feedback
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Solution Overview
Problem
Conventional language models, particularly large language models (LLMs), struggle with generating accurate program code in hardware description languages, often failing to implement all details of hardware module descriptions, especially state transition logic, and producing incorrect or asynchronously executing code.
Innovation Solution
A computer-implemented method involving a high-level planner agent to generate a plan from a natural language description, extract low-level circuit information, construct a task-driven circuit relation graph, and use a coding agent to generate and debug program code in hardware description languages, utilizing an abstract syntax tree-based waveform tracing for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional large language models are used to generate hardware description language code, then code generation speed is improved, but code accuracy and functional correctness deteriorate
Solution Approach 1:
The patent introduces an abstract syntax tree (AST) as an intermediary structure between the natural language description and the generated hardware code. The AST-based waveform tracing tool acts as a mediator that verifies the generated code against the original specification, ensuring accuracy while maintaining generation speed. This intermediary layer catches and corrects errors without requiring complete regeneration of the code.
Solution Approach 2:
The patent implements a feedback mechanism where the generated hardware description language code is automatically verified against the original natural language specification using AST-based waveform tracing. When discrepancies are detected, the system provides feedback to correct the code, ensuring functional correctness while maintaining efficient generation processes.
2Productivity
If conventional language models generate hardware description language code, then generation efficiency is improved, but implementation completeness of hardware details deteriorates
Solution Approach 1:
The patent performs preliminary extraction of hardware details and circuit information from the natural language description before code generation. By identifying and structuring hardware specifications in advance using AST representation, the system ensures that all hardware details are captured and preserved during the efficient code generation process, preventing information loss.
3Device complexity
If conventional language models are used for code generation, then simplicity of the generation process is maintained, but code reliability and defect reduction deteriorate
Solution Approach 1:
The patent implements a self-service verification mechanism where the generated code automatically validates itself against the original specification through AST-based waveform tracing. The system performs self-checks for functional correctness and automatically corrects defects without requiring external manual verification, thereby improving reliability while maintaining process simplicity.
Data Source
AI summary
A computer-implemented technique for generating program code includes receiving a natural language description of a hardware module, generating a first plan based on the natural language description, extracting first circuit information from the natural language description, generating a second plan based on the first plan and the first circuit information, and generating first program code in a hardware description language based on the second plan.