HDL Code Generation With AST Waveform Tracing for Functional Correctness
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Solution Overview
Problem
Conventional language models, particularly large language models (LLMs), struggle with generating accurate program code in hardware description languages, often failing to implement all details of hardware module descriptions, especially state transition logic, and producing incorrect or non-functional code.
Innovation Solution
A computer-implemented method involving a high-level planner agent to generate a plan, a circuit information extractor to identify low-level details, a graph construction module to integrate these into a task-driven relation graph, a coding agent to correct syntax errors, and a debugging agent using abstract syntax tree-based waveform tracing to correct functional errors, ensuring all details are accurately represented in the generated code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional large language models are used for code generation, then natural language processing capability is improved, but code accuracy and functional correctness deteriorate
Solution Approach 1:
The patent introduces an abstract syntax tree (AST) as an intermediary structure between natural language input and generated code. The AST-based waveform tracing tool analyzes simulation results and traces signal waveforms through the AST to identify functional errors, serving as a mediator that bridges the gap between high-level natural language descriptions and low-level code correctness verification.
Solution Approach 2:
The system implements a feedback loop where simulation results are fed back into the AST-based waveform tracing tool, which then identifies functional errors and uses this information to improve code generation. The traced waveform data provides feedback about timing and signal behavior issues that are corrected in subsequent code generation iterations.
2Productivity
If conventional LLMs generate hardware description language code, then code generation speed is improved, but implementation of detailed hardware logic deteriorates
Solution Approach 1:
The patent performs preliminary action by constructing an abstract syntax tree from the natural language description before code generation. The AST-based waveform tracing tool pre-analyzes the intended hardware behavior and signal timing requirements, allowing the code generator to produce more accurate hardware description language code that correctly implements detailed logic from the outset.
Solution Approach 2:
The patent segments the code generation process into distinct phases: natural language parsing, AST construction, waveform tracing analysis, and code generation. This segmentation allows each component to specialize in specific aspects of hardware logic implementation, improving overall precision while maintaining productivity through automated processing of each segment.
3Loss of time
If automated code generation is used, then development time is reduced, but functional correctness and defect rate deteriorate
Solution Approach 1:
The patent replaces manual mechanical debugging processes with automated AST-based waveform tracing. Instead of manually simulating and tracing waveforms to find functional errors, the system automatically constructs the AST, runs simulation, traces waveforms through the AST, and identifies errors programmatically, maintaining fast automated generation while improving functional correctness.
Data Source
AI summary
A computer-implemented technique for generating program code includes receiving a natural language description of a hardware module, generating a first plan based on the natural language description, extracting first circuit information from the natural language description, generating a second plan based on the first plan and the first circuit information, and generating first program code in a hardware description language based on the second plan.