Pre-Silicon HDL Debug via Automated Trace File Segmentation

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Solution Overview

Problem

Debugging tests for logic designed in hardware description language (HDL) is a cumbersome process, particularly in pre-silicon verification, due to the limitations of relying on verbose messages and debugger breakpoints, which are inefficient and often require rerunning tests, making it difficult to trace method calls, event occurrences, and thread information effectively.

Innovation Solution

Automatically generating a methods_extend.e file that logs complementary data such as method calls, event occurrences, parameter values, and thread information, allowing for a separate log review using a dedicated Graphical User Interface (GUI), which is available in both batch and interactive modes without polluting the regular log and requiring no rerun of tests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If debug messages are added to the code, then debugging information is obtained, but the log file becomes unreadable due to too many messages

Engineering Contradiction:
Improvedebugging informationVSAvoidlog file readability
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent segments debugging information into two separate channels: a filtered log file containing only selected debug messages, and a trace file containing comprehensive execution data including method calls, event occurrences, and thread information. This segmentation allows developers to choose the appropriate data source based on their specific debugging needs without being overwhelmed by excessive information in a single log file.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary filtering mechanism that selectively processes debug messages before writing them to the log file. This intermediary layer filters out unnecessary verbose information while preserving critical debugging data, thereby maintaining log file readability while still providing essential debugging information.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of information

If breakpoints are used throughout the code, then debugging information can be obtained, but the test needs to be rerun which wastes time

Engineering Contradiction:
Improvedebugging informationVSAvoidtest rerun time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent implements preliminary action by automatically generating a trace file during the initial test execution that captures comprehensive debugging information including all method calls, event occurrences, and thread information. This preliminary capture of data eliminates the need to rerun tests when adding breakpoints, as all necessary debugging information is already recorded in the trace file from the first execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a copy of the execution data in the trace file that mirrors what would be obtained through traditional breakpoint debugging. This copy contains sufficient debugging information to replace the need for actual breakpoint execution, allowing developers to analyze test behavior without rerunning the test with breakpoints set.

Inventive Principle:
Principle #26Copying

3Loss of information

If debug messages are added to the code, then method call information is obtained, but write permissions are needed and the code is locked to debuggers

Engineering Contradiction:
Improvemethod call informationVSAvoidcode modification requirement
Core Design Contradiction:
Loss of informationVSEase of manufacture

Solution Approach 1:

The patent introduces an intermediary trace analysis tool that automatically instruments the verification environment code to capture method call information without requiring direct modification of the original code. This intermediary tool intercepts and records execution data during test runtime, providing comprehensive debugging information while maintaining the integrity and lock status of the original verification environment code.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements self-service by having the verification environment automatically generate and maintain the trace file during normal test execution. The system instruments itself to capture execution data without external intervention or code modifications, allowing debugging information to be obtained autonomously during the original test run.

Inventive Principle:
Principle #25Self-service

4Loss of information

If verbose messages are used in test code, then event occurrence information is obtained, but the messages are hard to comprehend and complex to locate

Engineering Contradiction:
Improveevent occurrence informationVSAvoidmessage comprehension and location
Core Design Contradiction:
Loss of informationVSEase of operation

Solution Approach 1:

The patent segments event occurrence information into structured trace data with clear metadata including timestamps, thread identifiers, and hierarchical method call contexts. This structured segmentation makes it easy to comprehend and locate specific events by filtering and searching the trace file based on these organized attributes, rather than searching through unstructured verbose log messages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent replaces the mechanical system of reading and parsing unstructured log messages with an automated trace analysis system that can efficiently search, filter, and present event occurrence information based on structured criteria. This substitution enables rapid location and comprehension of events through automated querying of the trace file rather than manual log analysis.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9734263B2Method and apparatus for efficient pre-silicon debug
Publication Date: 2017.08.15 INTEL CORP
  • US9734263B2 patent drawing
  • US9734263B2 patent drawing
  • US9734263B2 patent drawing

AI summary

Described is a method and apparatus for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing an architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit, recognizing method calls associated with the architectural verification environment, and generating a list of recognized method calls that is loaded for a debug program to debug the HDL architecture of the integrated circuit.