HDL Execution via Data Flow Separation on Microprocessors
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Solution Overview
Problem
Conventional processor-based approaches for implementing Hardware Description Language (HDL) descriptions are hindered by high performance and power consumption issues due to the need for heavy data traffic and complex interconnects, making them less viable alternatives to ASICs or FPGAs for hardware realization.
Innovation Solution
The approach involves compiling HDL descriptions into executable programs for general-purpose microprocessors, separating data flow and control flow operations, and using complex processors to reduce data traffic and interconnect requirements, allowing for efficient execution of arithmetic and logic operations with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional processor-based approaches are used to execute HDL descriptions, then flexibility and reconfigurability are improved, but performance deteriorates due to heavy data traffic and complex interconnect requirements
Solution Approach 1:
The patent replaces the mechanical data movement approach (where results are stored and retrieved from memory between processing steps) with a direct functional connection approach. Processing elements are interconnected through a network that allows direct data flow between operations, eliminating the need for intermediate storage and retrieval cycles. This substitution of the data movement mechanism resolves the contradiction by maintaining flexibility through programmable processing elements while achieving ASIC-like performance through direct interconnections.
2Ease of manufacture
If conventional processor-based approaches are used to execute HDL descriptions, then ease of implementation is improved, but power consumption deteriorates due to heavy data traffic
Solution Approach 1:
The patent substitutes the high-power memory access mechanism with a low-power direct data path mechanism. Instead of storing results in memory and retrieving them for subsequent operations, processing elements exchange data directly through the interconnect network. This eliminates the energy-intensive read/write cycles to memory, resolving the contradiction by maintaining ease of implementation through programmable elements while dramatically reducing power consumption.
3Device complexity
If simple processing elements are used in processor-based approaches, then device complexity is reduced, but performance deteriorates due to multiple processors and clock cycles required for complex logic functions
Solution Approach 1:
The patent segments the processing system into multiple simple processing elements that are interconnected through a network. Each processing element remains relatively simple in structure, but the collective system achieves complex functionality through the combination of multiple elements working in parallel. The interconnect network enables these simple elements to execute complex logic functions in fewer clock cycles by allowing direct data flow between them, resolving the contradiction between element simplicity and system performance.
Data Source
AI summary
In one embodiment, a hardware implementation of an electronic system may be realized by compiling the HDL description into an executable form and executing the processor instructions. By applying data flow separation technique, the operations of the system can be effectively mapped into the instruction set of complex processors for efficient logic evaluation, in some implementations. An array of interconnected processors may be deployed, in some embodiments, to exploit the inherent parallelism in a HDL description.