HDL Fork-Join Block Transformation via Synchronized Free-Running Processes
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Solution Overview
Problem
The simulation of parallel fork-join blocks in hardware description languages (HDLs) poses challenges due to the need for dynamic memory allocation and thread creation, leading to increased processing overhead and synchronization complexities.
Innovation Solution
Transforming fork-join blocks into synchronized concurrent processes by creating free-running processes with timing constructs controlled by a single synchronization variable, allowing for concurrent execution without thread creation and minimizing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If threads are created for each sub-statement in fork-join blocks, then concurrent execution is achieved, but processing overhead and memory requirements increase
Solution Approach 1:
The patent creates a simplified copy of the parent process for each sub-statement, where each copy contains only the necessary sub-statement and synchronization variables. This avoids the need for full thread creation while maintaining concurrent execution capability. The copied processes share the same memory space and synchronization mechanism, reducing overhead compared to actual thread creation.
Solution Approach 2:
The patent segments the parent process into multiple independent copies, each responsible for executing a specific sub-statement. This segmentation allows concurrent execution without requiring full thread management infrastructure. Each segmented process can be independently scheduled and synchronized using shared variables, reducing the complexity of process management.
2Productivity
If threads are created for each sub-statement, then parallel execution is achieved, but memory requirements increase
Solution Approach 1:
The patent merges the memory spaces of all process copies by using shared synchronization variables. Instead of each thread having its own memory space, all processes share common memory for variables used in synchronization. This merging approach maintains parallel execution capability while significantly reducing memory requirements compared to separate thread stacks and memory spaces.
3Adaptability or versatility
If simulation kernel is modified to dynamically allocate memory and time, then fork-join block execution is enabled, but kernel complexity increases
Solution Approach 1:
The patent implements self-service by allowing processes to manually manage synchronization through shared variables without requiring kernel intervention. Processes use wait-on-variable constructs to synchronize their execution, eliminating the need for complex kernel-level dynamic allocation and scheduling mechanisms. This approach enables fork-join block execution while keeping the simulation kernel simple and unchanged.
4Duration of action of stationary object
If multiple threads are spawned for Always processes, then continuous execution is achieved, but processing overhead increases
Solution Approach 1:
The patent introduces dynamic scheduling where process copies are created and activated only when needed, rather than maintaining persistent threads. The simulation kernel dynamically allocates time slices to process copies based on their completion status and synchronization requirements. This dynamic approach enables continuous execution of Always processes while minimizing processing overhead by avoiding unnecessary thread management operations.
Data Source
AI summary
The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications in the simulation kernel. This transformation is done in such a way that the parallel behavior is retained in its entirety, and the same simulation time-relative results are produced. The concept of concurrency of processes inherent in HDL languages, including System Verilog, is utilized to achieve the same simulation results via the transformed HDL code, which uses the non-parallel block subset of System Verilog HDL.