HDL Code Generation via Genealogy Graph Tracing

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Solution Overview

Problem

Current systems for generating optimized hardware description language (HDL) code for hardware design lack efficiency in automatically satisfying constraints related to timing, area, and power consumption, as they fail to effectively identify and address performance bottlenecks in hardware synthesis.

Innovation Solution

A workflow that includes a modeling environment and a synthesis tool chain, where an initial in-memory representation of a model is transformed into a final form suitable for HDL code generation, with back-annotation of performance characteristics and iterative optimization techniques applied to meet specified constraints, using a genealogy graph to trace and optimize performance data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If automated HDL code generation is implemented, then productivity is improved, but manufacturing precision (timing, area, power constraints) deteriorates due to inability to effectively identify and address performance bottlenecks

Engineering Contradiction:

Improveautomated HDL code generation efficiencyVSAvoidconstraint satisfaction (timing, area, power)

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The system implements feedback by obtaining performance characteristics from the synthesis tool chain and mapping them back to nodes in the in-memory representation. This closed-loop feedback enables the code generator to identify performance bottlenecks and iteratively optimize the HDL code generation process to satisfy timing, area, and power constraints while maintaining high productivity

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system performs preliminary action by transforming the initial in-memory representation into a final form suitable for HDL code generation before actual code emission. This preliminary transformation phase allows for optimization of the representation structure to ensure constraint satisfaction in the final generated code

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If performance characteristics are traced back to initial in-memory representation, then manufacturing precision is improved, but device complexity increases due to genealogy graph construction and maintenance

Engineering Contradiction:

Improveperformance bottleneck identification accuracyVSAvoidgenealogy graph structure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The genealogy graph serves as an intermediary data structure that bridges the synthesis tool chain output and the initial in-memory representation. It mediates the complex task of tracing performance characteristics back to original model elements, enabling accurate bottleneck identification without directly exposing the complexity of the tracing mechanism to the user

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If iterative optimization is applied, then manufacturing precision is improved, but loss of time increases due to multiple transformation and synthesis iterations

Engineering Contradiction:

Improveconstraint satisfaction levelVSAvoidoptimization iteration time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The system implements dynamics by making the optimization process adaptive and iterative. The code generator dynamically adjusts the in-memory representation based on performance feedback, applying transformations and optimizations in multiple passes until constraints are satisfied, allowing the system to respond to varying complexity and constraint requirements

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10261760B1Systems and methods for tracing performance information from hardware realizations to models

Publication Date: 2019.04.16 MATHWORKS INC

AI summary

Systems and methods trace performance data generated by a hardware synthesis tool chain to model elements of a model. During code generation, an initial in-memory representation is generated for the model. The in-memory representation includes a plurality of nodes that correspond to the model elements. The in-memory representation is subjected to transformations and optimizations creating transitional in-memory representations and a final in-memory representation from which HDL code is generated. A graph builder constructs a genealogy graph that traces the transformations and optimizations. The genealogy graph includes graph objects corresponding to the nodes of the in-memory representations. The synthesis tool chain utilizes the HDL code to perform hardware synthesis. The synthesis tool chain also generates performance data. Utilizing the genealogy graph, the performance data is mapped to the nodes of the initial in-memory representation, and to the elements of the model.