HDL Model Partitioning for FPGA Emulation Latency
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Solution Overview
Problem
Existing methods for verifying the operation of electronic circuits designed using hardware-description languages (HDL) are inefficient in terms of speed, complexity, size, power consumption, and build time, particularly when implemented on programmable hardware like FPGAs.
Innovation Solution
The approach involves transforming HDL models into optimized forms using techniques such as circuit-element transformations, model-partitioning, and signal remapping, which reduce the number of circuit elements and area required for emulation, and utilize sequences of storage elements to manage latency and stalls, thereby enhancing emulation speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional HDL models are used for emulation, then the emulation can be implemented, but the speed is slow and complexity is high
Solution Approach 1:
The patent applies parameter changes by transforming the HDL model into a transformed HDL model with modified parameters. This includes changing the representation of circuit elements, adjusting timing parameters, and optimizing signal flow characteristics to achieve faster emulation while reducing complexity
Solution Approach 2:
The patent segments the HDL model into partitions, dividing the circuit into manageable sections that can be emulated more efficiently. This segmentation allows for reduced complexity by processing smaller subsets of the circuit independently
2Area of stationary object
If traditional HDL models are used for emulation, then the emulation can be implemented, but the size of the emulation system is large
Solution Approach 1:
The patent merges similar circuit elements and consolidates redundant components in the transformed HDL model. This merging reduces the overall area required for emulation while maintaining functional equivalence, directly addressing the size reduction goal
Solution Approach 2:
The patent extracts unnecessary or redundant components from the original HDL model during transformation. By removing elements that do not contribute to the core functionality, the emulation area is reduced while preserving essential circuit behavior
3Use of energy by stationary object
If traditional HDL models are used for emulation, then the emulation can be implemented, but power consumption is high
Solution Approach 1:
The patent changes operational parameters of the emulated circuit, including timing characteristics and signal transitions, to optimize power consumption. The transformed model incorporates power-aware parameter adjustments that reduce energy usage while maintaining correctness
4Loss of time
If traditional HDL models are used for emulation, then the emulation can be implemented, but build time is long
Solution Approach 1:
The patent performs preliminary transformation of the HDL model before emulation to pre-optimize the circuit structure. This preliminary action includes pre-computing timing parameters, pre-organizing circuit partitions, and pre-resolving dependencies, which significantly reduces build time during actual emulation
Data Source
AI summary
A system and method transforms a model of electronic circuit to improve emulation speed and/or reduce emulation area. The model may be divided into partitions; a sequence of storage elements may be created on a partition boundary to allow a partition to process the contents of the storage elements. The disposition of the sequence may correspond to a connection between hardware emulation elements to compensate for latencies therebetween.