HDL Model Partitioning for Efficient Signal Trace Resimulation
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Solution Overview
Problem
The existing simulation methods for hardware-description language (HDL) models of electronic circuits are inefficient as they require rerunning the entire simulation to capture signal traces, leading to reduced simulation speed and increased storage requirements.
Innovation Solution
The proposed solution involves predicting portions of the HDL model likely to be of future interest and caching corresponding simulation data. This allows for resimulation of specific portions without rerunning the entire model, optimizing simulation speed and storage usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the entire HDL model simulation is rerun to capture signal traces, then complete signal trace data is obtained, but simulation speed decreases and storage requirements increase
Solution Approach 1:
The patent divides the HDL model into multiple partitions and selectively resimulates only those partitions containing signals of interest. This segmentation allows verification engineers to obtain complete signal trace data for specific signals without rerunning the entire model, thus maintaining data completeness while improving simulation speed and reducing storage requirements.
Solution Approach 2:
The patent implements a caching mechanism that stores simulation data from previous simulation runs. When signal traces are needed, the system checks the cache first and retrieves stored data if available, avoiding the need to rerun simulations. This preliminary action of caching data significantly reduces simulation time and storage requirements while maintaining data completeness.
2Loss of information
If the entire HDL model simulation is rerun to capture signal traces, then complete signal trace data is obtained, but storage requirements increase
Solution Approach 1:
The patent segments the HDL model into partitions and only resimulates or caches data for partitions containing signals of interest. This selective approach reduces the total volume of simulation data that needs to be stored while ensuring complete trace data is available for the specific signals being verified, thus reducing storage requirements without sacrificing data completeness.
Solution Approach 2:
The caching mechanism stores simulation data in advance, allowing retrieval without rerunning simulations. This preliminary action reduces the need for repeated full simulations and their associated storage requirements, while maintaining complete signal trace data availability through selective caching of relevant partitions.
3Measurement precision
If signal traces are captured during full simulation, then verification data is obtained, but simulation speed is reduced
Solution Approach 1:
The patent implements partitioning of the HDL model to isolate only the relevant portions containing signals of interest. By resimulating only these specific partitions rather than the entire model, the system maintains accurate signal trace data for verification while significantly improving simulation speed through reduced computational scope.
Solution Approach 2:
The system caches simulation data from previous runs and retrieves it when signal traces are needed, rather than rerunning simulations. This preliminary caching action ensures accurate signal trace data is available for verification while avoiding the simulation speed reduction that would occur with repeated full simulations.
Data Source
AI summary
A system and method allows resimulation of a portion of a model of an electronic circuit. The system and model may predict and cache data associated with the resimulation of the portion (e.g., the initial state and input signals associated with the portion) in a computer memory. If a request is received to resimulation the portion, the system and method may use the cached data to perform the resimulation.