HDL Port Memory Allocation for Simulation Efficiency
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Solution Overview
Problem
Existing HDL-based circuit design simulation methods require significant memory and computation resources due to separate memory allocation for formal and actual ports without considering compatibility, leading to inefficient simulation performance.
Innovation Solution
Allocate memory locations for formal and actual ports based on compatibility, sharing a single memory location for compatible ports and using separate locations for incompatible ones, with simulation code optimized to update values using single or respective operations accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory locations are allocated for formal and actual ports, then memory safety and correctness are ensured, but memory usage and computation resources increase significantly
Solution Approach 1:
The patent merges the memory allocation for formal and actual ports by checking compatibility between them. When compatible, both formal and actual ports share the same memory location through a single allocated pointer, eliminating redundant memory usage while maintaining correctness through compatibility verification
Solution Approach 2:
The patent applies different memory allocation strategies based on local compatibility characteristics. Each port connection is evaluated individually for compatibility between formal and actual types, allowing selective sharing of memory locations where compatible while maintaining separate allocations where incompatible, optimizing memory usage locally throughout the design
2Reliability
If separate memory locations are allocated for formal and actual ports, then data correctness is maintained, but the number of update operations increases
Solution Approach 1:
The patent combines update operations for compatible formal and actual ports by allocating a single memory location. When a value needs to be updated, the operation is performed once on the shared memory location, automatically updating both formal and actual ports simultaneously, thereby reducing the total number of update operations and improving simulation performance
Solution Approach 2:
The patent changes the parameter of memory allocation from separate dedicated locations to shared compatible locations. This parameter change in the allocation strategy enables the system to reduce update operations while maintaining data correctness through type compatibility verification
Data Source
AI summary
A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.