HDL Simulation Memory Allocation for Singly-Driven Nets
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Solution Overview
Problem
Existing HDL simulators generate simulation code that is general enough to handle both singly-driven and multiply-driven nets, leading to inefficient data structures and increased memory access during runtime, which negatively impacts simulation performance.
Innovation Solution
The method involves determining whether nets are singly-driven or multiply-driven during compilation and allocating specific memory locations or blocks for driver values, generating simulation code that optimally stores and retrieves these values, reducing memory access and computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general data structures are used to handle both singly-driven and multiply-driven nets, then the simulation code can handle all cases, but memory usage and computational complexity increase
Solution Approach 1:
The patent segments the handling of nets into two distinct categories: singly-driven nets and multiply-driven nets. During compilation, the simulator identifies which category each net belongs to and generates specialized code for each type. This segmentation allows the use of simple, efficient data structures for singly-driven nets while using more complex structures only where necessary for multiply-driven nets, thereby reducing overall complexity.
Solution Approach 2:
The patent applies local quality by using different data structure characteristics for different parts of the simulation based on their specific needs. Singly-driven nets use straightforward storage mechanisms, while multiply-driven nets use more sophisticated structures capable of handling multiple drivers. This localized optimization ensures that each part of the system uses the minimum necessary complexity to handle its specific requirements.
2Adaptability or versatility
If general data structures are used to handle both singly-driven and multiply-driven nets, then the simulation code can handle all cases, but memory access time increases
Solution Approach 1:
The patent segments memory access patterns based on net type. For singly-driven nets, the compiler generates direct memory access code that reads and writes driver values without complex resolution logic. For multiply-driven nets, the compiler generates optimized access patterns that batch multiple driver values together and apply resolution functions efficiently. This segmentation reduces the average memory access time across the entire simulation.
Solution Approach 2:
The patent performs preliminary analysis during the compilation phase to identify which nets are singly-driven and which are multiply-driven. Based on this analysis, the compiler pre-generates optimized access code for each type, avoiding the need for runtime determination and complex memory access patterns. This preliminary action ensures that the most efficient memory access path is used for each net from the start of simulation.
3Adaptability or versatility
If runtime determination of net types is performed, then the simulation can adapt to actual circuit behavior, but compilation time benefits are lost and runtime overhead increases
Solution Approach 1:
The patent performs the net type determination action during the compilation phase rather than at runtime. The compiler analyzes the HDL source code and statically identifies which nets are singly-driven and which are multiply-driven, generating specialized code for each type before simulation begins. This preliminary action eliminates runtime overhead while maintaining adaptability to the specific circuit being simulated.
Solution Approach 2:
The patent creates separate code paths or templates for handling singly-driven and multiply-driven nets. Instead of using a single general-purpose handler that must work for all cases, the compiler generates specialized code copies optimized for each specific net type. This copying approach allows the simulation to adapt to the actual circuit characteristics while maintaining high performance through specialized code paths.
Data Source
AI summary
A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.