HDL Simulation Threshold-Filtered Event Counting

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Solution Overview

Problem

In digital design processes, simulating complex logic networks is challenging due to the need for verifying logical correctness before actual fabrication, as traditional methods are inefficient and costly, especially when dealing with integrated circuits.

Innovation Solution

A method and system utilizing a hardware description language (HDL) simulation model with instrumentation modules to monitor design parameters, allowing for accurate and comprehensive monitoring of digital circuit designs without compromising performance, by counting occurrences of specific events and applying thresholds to discard non-significant data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If all event occurrences are recorded during simulation, then measurement precision is improved, but loss of time increases due to processing large volumes of non-significant data

Engineering Contradiction:
Improveevent count accuracyVSAvoiddata processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by establishing minimum thresholds for event counting before the simulation executes. The counter is configured with a threshold value, and the simulation engine compares each event count against this threshold during simulation, only recording results that meet or exceed the threshold. This pre-established criterion eliminates the need to process and store all event data, significantly reducing post-simulation data processing time while maintaining accurate measurement of significant events.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If comprehensive monitoring of all design parameters is implemented, then measurement precision is improved, but device complexity increases due to additional instrumentation

Engineering Contradiction:
Improvedesign verification accuracyVSAvoidinstrumentation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by implementing selective monitoring of specific design parameters rather than comprehensive monitoring of all parameters. The simulation engine allows users to specify particular events and counters of interest, applying monitoring resources only to those specific locations in the design where measurement is needed. This targeted approach maintains high measurement precision for critical parameters while avoiding the complexity overhead of monitoring every possible design parameter.

Inventive Principle:
Principle #3Local quality

3Measurement precision

If detailed simulation data is collected for all events, then measurement precision is improved, but productivity decreases due to increased computational load

Engineering Contradiction:
Improvesimulation result accuracyVSAvoidsimulation execution speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies the extraction principle by separating significant events from non-significant events during simulation processing. The threshold-based filtering mechanism extracts only those event counts that meet the predetermined significance criteria, discarding or ignoring the majority of events that do not meet the threshold. This extraction of relevant data from the total event stream maintains measurement precision for important events while dramatically reducing the computational load associated with processing and storing all event data, thereby improving simulation execution speed and overall productivity.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7925489B2Defining and recording threshold-qualified count events of a simulation by testcases
Publication Date: 2011.04.12 SIEMENS INDUSTRY SOFTWARE INC
  • US7925489B2 patent drawing
  • US7925489B2 patent drawing
  • US7925489B2 patent drawing

AI summary

A design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and the simulation includes counting occurrences of the count event in the count event counter to obtain a count event value. A threshold is also established for an aggregate count event value for the count event counter. After completion of the testcase, a determination is made whether addition of the count event value to the aggregate count event value for the count event counter would cause the aggregate count event value to exceed the threshold. If not, the count event value is recorded in a testcase data storage area, and the count event value is accumulated in the aggregate count event value. If so, the count event value is discarded without recording the count event value in the testcase data storage area.