HDL Simulator Event Merging for Delta Cycle Performance
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Solution Overview
Problem
Current HDL simulation techniques face performance bottlenecks due to the large number of events scheduled during each delta cycle, which significantly impact runtime performance, as thousands to hundreds of thousands of events need to be processed and scheduled, leading to increased computing resources and time.
Innovation Solution
Implementing an HDL simulator scheduler that merges events for the same signal within a delta cycle based on specific conditions, such as overlapping or adjacent bit ranges, to reduce the number of events scheduled, thereby improving runtime performance by combining signal assignments into a single merged event.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional HDL simulation schedules all events individually during each delta cycle, then simulation accuracy is maintained, but runtime performance deteriorates due to processing thousands to hundreds of thousands of events
Solution Approach 1:
The patent merges multiple events for the same signal within a delta cycle into a single consolidated event when their bit ranges overlap or are adjacent. This reduces the total number of events from thousands to hundreds of thousands down to a much smaller set, significantly improving runtime performance while preserving simulation accuracy by maintaining all necessary signal updates within the merged event structure.
2Productivity
If the number of events scheduled during each delta cycle is reduced through merging, then runtime performance improves, but event scheduling complexity increases
Solution Approach 1:
The patent segments the event merging process into distinct phases: identifying events for merging, determining mergeability based on bit range overlap or adjacency, consolidating the events, and scheduling the merged result. This structured segmentation of the scheduling process makes the complexity manageable and systematic rather than chaotic.
Solution Approach 2:
The patent performs preliminary analysis of event bit ranges before final scheduling to identify which events can be merged. By pre-processing events to determine their mergeability based on overlapping or adjacent bit ranges, the system reduces the scheduling burden that would otherwise occur during the critical simulation execution phase.
3Productivity
If events are merged based on overlapping bit ranges, then the number of scheduling operations decreases, but the risk of merging incompatible events increases
Solution Approach 1:
The patent applies local quality control by examining the specific bit ranges of each event to determine mergeability. Events are only merged when their bit ranges overlap or are adjacent, ensuring that the merge operation is appropriate for the local characteristics of the signals involved. This localized verification prevents incompatible events from being merged while allowing compatible ones to be consolidated.
Data Source
AI summary
Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.